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Содержание Super Quad S-100

Страница 1: ...THE WORLD S FIRST S 100 Single Board Computer TECHNICAL MANUAL for SUPER QUAD 12700 8 Knott Avenue Garden Grove CA 92641 TELE 714 891 4004 TELEX 678401 Tabirin...

Страница 2: ...runs with TURBO LOS Un The SUPER QUAD SEC contains 1 Z 80A cpu 4 MHZ 2 Floppy disk controller up to 4 drives 8 or 5 i 3 64K of dynamic merrory 16K bank selectible 4 2K or 4K of shadow eprom 2716 or 27...

Страница 3: ...IO parallel port channel A 11 4 4 PIO parallel port channel B 11 4 S Control timet Interrupt circuit 11 4 6 Floppy Disk controller 11 4 7 Floppy disk control port 12 4 8 Extended address port 13 4 9 O...

Страница 4: ...n 5 25 inch drive configuration Shugart 800 drive sl lugart 850 MP I d r i v e MFE n 0 del 7 0 0 TANDON SLIM LINE NEC model FDl160 QUME Data Track 8 l ANDON 5 1 4 27 28 29 30 31 11 0 Appendex Data she...

Страница 5: ...32K 48K 48K 64K under software control This allows the CPU to access bank switchable external memory on the 8100 bus The memory has an access time of 2000s Refresh is done during Z80 Ml cycles and du...

Страница 6: ...s plus a variety of interrupt modes Modem control signals are available at each serial connector There are two switch selectible baud rate generators for baud rates of 50 to 19 2 k baud Note The seria...

Страница 7: ...eader for synchronous baud rates or long clock times 1 S100 Bus Inter face The Sl00 bus interface provides the signals necessary for an 8 bit bus master as described by the IEEE 696 bus specification...

Страница 8: ...d 2 1 Eprom Enable Disable Switching EPROM on F033 3E4F MVI A l001l11B iRESET POWER ON JUMP i AND ENABLE MEMORY EPROM ON F035 0316 OUT 168 iWRITE TO CONTROL PORT Switching EPROM off F033 3E4F MVI A 01...

Страница 9: ...me drive Track 0 sector 1 will be read into memory at location 0 Single densi y is assumed for track 0 If an error occures an error code will be printed The error code must be translated using the tab...

Страница 10: ...T SECTOR F4D9 3EBC MVI A 08CB GET READ COMMAND F4DB 030C ou r FOC ISSUE COMMAND F4DD 0 Nap FDCRD E 4DE DB14 IN WAIT WAI 1 FOR INTRQ F4E0 B7 ORA A OR ORQ F4El F2EBF4 JP BOOTDN EXIT I F I N 1 RQ F4E4 DB...

Страница 11: ...Control Port PlO Channel A Data port PIO Channel B Data port PIa Channel A Control port PlO Channel B Control Port CTC Channel 0 Control Port CTC Channel 1 control Portal CTC Channel 2 Control Port eT...

Страница 12: ...O Channel A Control POlt See Appenoix B I his port can be jumpered via jumpers E through P to the 5100 Vedtoted Interrupt lines or to connector J2 see sec 6 0 05 07 Read Write Wti t e PIO Channel B Da...

Страница 13: ...he floppy disk controller INTRQ status bit is placed on the data bus as bit 07 This bit can be tested to determine if data is to be transfered of if the command is complete D7 D6 D5 D4 D3 D2 D1 1 DO 1...

Страница 14: ...D0 Disk drive select bit Dl SIDE SELECT 0 HEAO 0 1 HEAO 1 Density 0 single l double Don t care Don t care Don t care Don t care 4 8 Extended address port 15 Write See Section 8 1 buss defination S100...

Страница 15: ...of this port switches the on board EPROM on and off The onboard EPROM occupies address F000H FFFFH The EPROM is switched on automatically during reset or power on the EPROM contains SID and Foe initi...

Страница 16: ...intcLrupt vector VIS or Parallel Port B bit D5 on J2 35 G Select 5100 interrupt vector VI6 ot Parallel Port B bit 06 on J2 37 F 5 lect 8100 interrupt vector VI7 or Parallel Port B bit D7 on J2 39 R S...

Страница 17: ...use in sycronous applications Jumper C is located near J5 1 1 Connector J5 pin 9 SIO TX Rx clock input 1 3 Baud rate generator channel B Install Plug between posts I 2 fOl external SIO clock Install...

Страница 18: ...r connector J2 l f 1 1 12131 I nstall pI ug between posts 1 f 2 to connect the PIO bi t D to J2 pin 25 when the PIO bit is prugrammed for input output Install Plug between posts 2 3 to connect the PIO...

Страница 19: ...nstall Plug between posts 1 2 to connect the PIO bit 03 to J2 pin 25 when the PIO bit is programmed for input output Install Plug between posts 2 3 to connect the PIO bit 03 to the vectored interrupt...

Страница 20: ...posts 1 2 to connect the PlO bit 06 to J2 pin 25 when the PIO bit is programmed for input output Install Plug betw cen posts 2 3 to connect th PlO bit D6 to the vectored interrupt line VI6 wherl the P...

Страница 21: ...always addressed at F800H and can not be moved Since the 2716 EPROM is 2K long it appears twice E800H FC00H and FBFFH FFFFH 6 15 S Define floppy disk connector for eight five inch drives and FDC chip...

Страница 22: ...1 2 3 4 set the baud rate for the 510 channel witches 5 6 7 8 set the baud rate for the SIO channel OFF up SWl 8 7 6 5 4 3 2 1 ON down Channel B Channel A 7 1 Baud rate switch setting Switch Switch 8...

Страница 23: ...3 59 VI4 60 VI5 61 64 VI6 65 65 VI7 67 NMI 68 PWRFAI L 69 DMA3 70 A18 71 A17 72 A16 73 SDSB 74 CDSB 75 GND 76 NDEF 77 ADSB 78 DODSB 79 87 o 88 95 PSTVAL 96 PHLDA 97 RFU 98 A5 A4 A3 A15 A12 A9 DOl DATA...

Страница 24: ...bit D6 18 PA6 RE l ground 19 PA7 PIO Channel A data bit D7 20 PA7 RET ground 21 BRDY PIO Channel B t eady signol 22 BRDY RET gt ound 23 BS l RB PIO Channel B strobe 24 BSTRB RE l ground 25 PB0 PIO Ch...

Страница 25: ...5 ground 22 6 Ready 23 7 ground 24 8 Above 1 rack 43 A 25 9 ground 26 10 Drive select 0 27 11 ground 28 12 Drive select 1 29 13 ground 30 14 Drive select 2 31 15 ground 32 16 Drive select 3 33 17 gro...

Страница 26: ...inal ready 9 Tx RxCA Transrnitt receive clock 10 GND 11 N C 12 16 VOLTS 13 16 VOLTS 14 5 VOLTS 8 5 Connector J5 Serial port Channel B 1 N C 2 DCDA Data Carrer Detect Channe I A 3 SYNCA Sync Detect 4 R...

Страница 27: ...r 1 7 jumpersl 1 Parallel 1 ports 1 connector _ Floppy disk 1 controller t 1 conn 1 lconn 1 A Serial B 1 ports lclock eprom CPU 2k 4k 1 data rec l S100 address 1 drivers 1 drivers Ram Array VI lines S...

Страница 28: ...SIO A internal Tx Rx clock for SIO B internal Eight inch Drive selection Select vector line VI0 Parallel Port B bit D0 on J2 25 Parallel Port B bit Dl on J2 27 Parallel Port B bit D2 on J2 29 Paralle...

Страница 29: ...Parallel Port B bit D5 on J2 35 N 2 3 Parallel Port B bit D6 on J2 37 P 2 3 Parallel Port B bit D7 on J2 39 R 2 1 Select 2716 S 1 2 5 8 6 9 7 10 11 12 Define floppy disk connector T 1 2 Enable S100 b...

Страница 30: ...Jumper 28 Jumper C Jumper A Jumper B Jumper R Jumper I Jumper Y Jumper 850 IT F8 RM Jumper 82 Jumper Jumper Jumper Jumper Jumper S J umpe r vl OS Jumper FM MFM D81 for drive 1 and DS2 for drive 2 ins...

Страница 31: ...Install jumpers as follows Jumper C Jumper N Jumper HLS Jumper M Jumper PRI Jumper DLD Jumper E U 10 9 QUME data track 8 Disk drive jumpers Install jumpers as follows DSl OR DS2 CU1 X CUT Z CUT L INST...

Страница 32: ...11 0 ppendex Data sheets 11 1 Appendex A Z80A S10 DART 31...

Страница 33: ...IDA iiiCA TIDA TICA W RDVA RnA MODEM RiA CONTROL RID8 iiifiCIi TIDB MODEM C fH CONTROL DTRB DCli8 Figure 1 Z80 DART Pin Functions Z8470 Z80 DART Dual ASJllcbronous Recelver TraDSmiller Produel SpecUIc...

Страница 34: ...2 80 CPU active Low When MI and RD are both active the 2 80 CPU is fetching an instruction from memory when MI is active while IORO is active the 2 80 DART accepts MI and 10RQ as an interrupt acknowl...

Страница 35: ...nterrupt vectored or non vectored and Block Transfer modes to transfer data status and control information to DATA CONTROL CPU BUS 110 INTERRUPT CONTROL LINES ttt 5VGND CLK INTERNAL CONTROL LOGIC INTE...

Страница 36: ...ock transfers 2 80 DMA or other designs The Block Transfer mode uses the W RDY output in conjunction with the Wait Ready bits of Write Register 1 The W RDY output can be defined under software control...

Страница 37: ...rangement in addition to the 8 bit receive shift register This scheme creates additional time for the CPU to organize the programming process The logic for both channels provides for mats bit synchron...

Страница 38: ...ust been processed CLOCK CE _ _ _ _01 __ If M1 DATA G0 Figure 5a Read Cycle CLOCK M1 _ _ _ _ _ __II _ _ J 1 AD lEI 7 _ DATA Figure 5c Interrupt Acknowledge Cycle Status byte from the Z 80 DART are ill...

Страница 39: ...error conditions interrupt vector and standard communications interface signals To read the contents of a selected read register other than RRO the system program must first write the pointer byte to...

Страница 40: ...T CHARACTER 1 0 1 I STOP BITS CHARACTER 1 1 2 STOP BITS CHARACTER NOT USED o 0 Xl CLOCK MODE o 1 X18 CLOCK MODE 1 0 X32 CLOCK MODE 1 1 X64 CLOCK MODE READ REGISTER 2 Illli INTERRUPT V4 VECTOR V5 VB V7...

Страница 41: ...11 2 Appendex B Z80A PIO...

Страница 42: ...B_ lEO Figure 1 Pin Functions PORTA PORT B Z8420 Z80 PIO Parallel Input Output Controller Product Specification March 1981 Programmable interrupts on peripheral status conditions Standard 2 80 Family...

Страница 43: ...d The CPU can read the input data at any time which again sets Ready Mode 2 is bidirectional and uses Port A plus the interrupts and handshake signals from both pmts Port B must be set to Mode 3 and m...

Страница 44: ...ister specifies which of the bits in the port are active and which are masked or inactive INTERRUPT CONTROL LINES The mask control register specifies two conditions first whether the active state of t...

Страница 45: ...O decodes the RET Return From MODE CONTROL REGISTER 2 BITS Used In the bit mode only to allow generltlon 01 In 1 lerruplll Ihe peripheral 1 0 pins go 10 Ihe specified Itll Interrupt instruction direct...

Страница 46: ...sets the logic conditions and the logic levels required for gener ating an interrupt Two logic conditions or functions are available ANO if all input bits change to the active level an interrupt is tr...

Страница 47: ...al Device input active Low This signal is similar to ASTB except that in the Port A bidirectional mode this signal strobes data from the peripheral device into the Port A input register C O Control Or...

Страница 48: ...ther than the automatically inserted TWA Output Mode Mode 0 An output cycle Figure 14 is always started by the execution of an output instruction by the CPU The WR pulse from the CPU latches the data...

Страница 49: ...time new data can be loaded into the PIO Figure 15 Mode I Input Timing Bidirectional Mode Mode 2 This is a com bination of Modes aand 1 using all four hand shake lines and the eight Port A I O lines...

Страница 50: ...y chain The peripheral with lEI High and lEO Low during INTACK places a preprogrammed 8 bit interrupt vector on the data bus at this time Figure 18 lEO is held Low until a Return From Interrupt RET in...

Страница 51: ...AC Charac teristics 54 CLOCK Ci B A C O Do D7 OUT IN r _ ir ________ i M1 lEI lEO READY ARDY OR BRDY STROBE ASTB OR BSTB AO A7 Bo B7 MODEO MODE 1 MODE 2 MODE 3 12 1 2006 0332...

Страница 52: ...to Clock I Setup Time To Activate READY on Next Clock Cycle 220 200 170 20 TdC RDYr Clock 1 to READY I Delay 200 190 170 5 CL 50 pF 21 TdC RDYf Clock I to READY I Delay 150 140 120 5 22 TwSTB Pulse W...

Страница 53: ...sted under Absolute Maxi mum Ratings may cause permanent damage to the device This is a stress rating only operation of the device at any condition above those indicated in the operational sections of...

Страница 54: ...11 3 Appendex C Z80A CTC...

Страница 55: ...0 eTC Counlerl Timer Clrcllit Product Specification March 1981 III Selectable positive or negative trigger initiates timer operation Standard Z 80 Family daisy chain interrupt structure provides fully...

Страница 56: ...nals to the CTC for distribution on the internal bus FROM zao CPU DATA CONTROL a preset down counter Thus the time interval is an integral mul tiple of the clock period the prescaler value 16 or 256 a...

Страница 57: ...sable II Operating mode timer or counter Timer mode prescaler factor 16 or 256 II Active slope for CLK TRG input Timer mode trigger automatic or CLK TRG input Time constant data word to follow Softwar...

Страница 58: ...SELECTION oSELECTS FALLING EDGE 1 SELECTS RISING EDGE Do D7 go to the high impedance state All channels must be completely reprogramJIled after a hardware reset The software reset is controlled by bit...

Страница 59: ...l will not operate without a time constant value The only way to write a time constant value is to write a control word with 02 set I lS TC5 LTC2 TC TC3 Figure 6 Time Constant Word Software Reset Sett...

Страница 60: ...ce is being serviced INT Interrupt Request output open drain active Low Low when any Z 80 CTC channel that has been programmed to enable interrupts has a zero count condition in its down counter IORQ...

Страница 61: ...e of clock cycle TWA No additional wait states are allowed TIME INTERNAL START TIMING TIMZR Figure 11 Timer Mode Timing Timor Operation In the timer mode a CLK TRG pulse input starts the timer Figure...

Страница 62: ...Interrupt Acknowledge Timing were written to the CTC during the program ming process the next two bits are provided by the CTC interrupt control logic as a binary code that identifies the highest prio...

Страница 63: ...11 4 Appendex D Floppy Disk controller...

Страница 64: ...31 READY Dill 10 31 WO 0AI i 10 WG OAL5 12 29 TG 3 tI m l 13 i5AL1 27 STEP 15 OIRC 16 EARLY 17 LATE 18 W 19 22 lESf IGNOIVSS LL20 _ _ _ J 21 Vcc 5VI 791 3 RG 179517 SSO 79317 mUE BUS PIN CONNECTIONS C...

Страница 65: ...fabricated in N channel Silicon Gate MaS technology and is TTL compatible on all inputs and outputs The 1793 is identical to the 1791 except the DAL lines are TRUE for systems that utilize true data...

Страница 66: ...motors 23 HEAD LOAD TIMING HLT When a logic high is found on the HLT input the head is assumed to be engaged 25 READ GATE 1791 3 RG A high level on this output indicates to the data separator circuitr...

Страница 67: ...1 Pin 33 functions as a WF input If WF 0 any write command will im mediately be terminated When WG 0 Pin 33 func tionf 1 a VFOE output VFOE will go low during a read operation after the head has load...

Страница 68: ...of the type of command previously executed This register can be read onto the DAL but not loaded from the DAL CRC Logic This logic is used to check or to gener ate the 16 bit Cyclic Redundancy Check...

Страница 69: ...erfacing with the mini floppy the ClK input is set at 1 MHz for both single density and double density When the clock is at 2 MHz the stepping rates of 3 6 10 and 15 ms are obtainable When ClK equals...

Страница 70: ...used to inform phase lock loops when to acquire syn chronization When reading from the media in FM RG is made true when 2 byles of zeroes are detected The FD179X must find an address mark within the n...

Страница 71: ...Track 1 1 1 1 0 E 0 0 IV Force Interrrupt 1 1 0 1 IJ h II 10 Note Bits shown in TRUE form Table 3 FLAG SUMMARY TYPE I COMMANDS h Head Load Flag Bit 3 h 1 Load head at beginning h 0 Unload head at beg...

Страница 72: ...read off the disk The track address of the TYPE ICOMMAND FLOW 10 field is then compared to the Track Register if there is a match and a valid 10 CRC the verification is complete an interrupt is genera...

Страница 73: ...ve The stepping motor direction is the same as in the preyious step command After a delay determined by ther ro field a verification takes place if the V flag is on If the u flag is on the Track Regis...

Страница 74: ...3 and the command is terminated with an interrupt HOlE I i i Si II fH Af ISfrrIIO Ofl I TIn NOClK HI rHIERIISlOUSOElA f TYPE II COMMAND 341 Sector Length Table Soctor Length Number of Bytes Field hex...

Страница 75: ...ented in each sector For IBM compatability the b flag should be set to a one The TYPE II COMMAND s flag allows direct control over the sSe Une Pin 25 and is set or reset at the beginning of the comman...

Страница 76: ...re as sembled and transferred to the DR and it ORO is generated for each byte The six bytes of the 10 field are shown below Although the CRC characters are transferred to the computor the FD179X check...

Страница 77: ...MFM F5 Not Allowed Write A1 in MFM Preset CRC F6 Not Allowed Write C2 in MFM F7 Generate 2 CRC bytes Generate 2 CRC bytes Fa thru FB Write Fa thru FB Clk C7 Preset CRC Write Fa thru FB in MFM FC Write...

Страница 78: ...ENTER on TEST NO DELAY II TEST 1 and eLK 1 MHZ 30 MS DELAY INma RESET BUSY READ ADDRESS TYPE II COMMAND Read Track Address 345...

Страница 79: ...is the only command that will enable the immediate interrupt to clear on a subse quent Load Command Register or Read Status liegister STATUS DESCRIPTION Upon receipt of any command except the Force In...

Страница 80: ...reted as an ID address mark DATA FE CLK C7 and the CRC will be initialized An F7 pattern will generate two CRC characters in FM or MFM As a consequence the patterns F5 thru FE must not appear in the g...

Страница 81: ...s gapsize must be according to the following table Note that the Index Mark is not required by the 179X The minimum gap sizes shown are that which Is required by the 179X with Plliock up time motor sp...

Страница 82: ...ADDR CS to R 50 nsec THLD Hold AOOR CS from RE 10 nsec TRE RE Pulse Width 400 nsec CL 50 pf TORR ORa Reset from RE 400 500 nsec TIRR INTRa Reset from RE 500 3000 nsec See Note 5 TDACC Data Access fro...

Страница 83: ...DATA INTO SECTQA TRACK CIA OATA REGISTER USER CANNOT READ THIS REGr8TEA UHf AT LEAST 4 SEC IN MFa AnEA THE FUSING EOGE OF WE v RST CASEI i t TIME OOU8U S WHEN ClOCK IMHz WRITE ENABLE TIMING MIN TYP 50...

Страница 84: ...or4 J Lsec ClK Error Ts Early Late to Write Data 125 nsec MFM Th Early late From 125 nsec MFM Write Data Twf Write Gate off from WD 2 J Lsec FM 1 J Lsec MFM Twdl WD Valid to Clk 100 nsec ClK 1 MHZ 50...

Страница 85: ...IONS nsec nsec ILsec See Note 5 ILsec CLKERROR ILsec ILsec See Note 5 ILsec 1 Pulse width on RAW READ Pin 27 is normally 100 300 ns However pulse may be any width if pulse is entirely within window If...

Страница 86: ...f Write Precompensation circuits are mandatory for reliable data transfers Whether to go with 8 double density or not is dependent upon PC board space and the additional circuitry needed to ac curatel...

Страница 87: ...er has the option of checking the busy bit or use the INTRa Line to denote command comple tion The Busy bit will be reset whenever the 179X is idle and awaiting a new command The INTRa Line once set c...

Страница 88: ...pensation is a function of the drive Some manufacturers recommend Precompensating the 5114 drive while others do not With the 8 drive Precompensation may be specified from TRACK 43 on or in most cases...

Страница 89: ...nown pattern of one s or zero s then RG READ GATE can be used The RG signal will go active when the 179X is currently over a field of zeros or ones RG is not available on the 1795 1797 devices since t...

Страница 90: ...y used to terminate a multiple sector command or to insure Type I status in the status register The lower four bits of the command determine the conditional interrupt as follows 10 NOT READY TO READY...

Страница 91: ...0 218 750 5 SINGLE 2 3125 218 750 5114 DOUBLE 2 6250 437 500 8 SINGLE 1 5208 401 016 8 DOUBLE 1 10 416 802 032 8 SINGLE 2 5208 802 032 8 DOUBLE 2 10 416 1 604 064 Based on 35 Tracks Side Based on 18 S...

Страница 92: ...11 5 Appendex E Z80A CPU...

Страница 93: ...1 c I Z80 CPU Au CONTROL INT Au NMI Au A15 RESET CPU BUS CONTROL ClK 5V GND Figure 1 Pin Functions Z8400 Z80 CPU Central Processing Unit Product Specification March 1981 may be daisy chained to allow...

Страница 94: ...n or alternate registers accessible to the programmer The alternate set allows operation in foreground background mode or it may 5V GND CLOCK be reserved for very fast interrupt response The Z80 also...

Страница 95: ...URPOSE _8BITS _ _ 1 8 BITS IX INDEX REGISTER IY INDEX REGISTER SP STACK POINTER PC PROGRAM COUNTER I INTERRUPT VECTOR I R MEMORY REFRESH _ 8 B I T S _ A B D H each of which has an 8 bit prescaler Each...

Страница 96: ...xed addressing Same as IX above Stores addresses or data temporarily See Push or Pop in instruc tion set Holds address of next instruction Set or reset to indicate interrupt status see Figure 4 Reflec...

Страница 97: ...he data bus during the interrupt acknowledge cycle The high order byte of the interrupt service routine address is supplied by the I Interrupt register This flex ibility in selecting the interrupt ser...

Страница 98: ...A 0 X 0 X 0 LD DE A DE A 0 0 x x 0 LD nnl A nn A X X 0 LDA I A I I X 0 X IFF 0 LD A R A R I X 0 X IFF 0 LDI A I A X X 0 LDR A R A 0 0 x 0 x 0 NOTES r r means any of the registers A B C D E H L IFF the...

Страница 99: ...X SP 2 IXL X X 11 011 101 DD 15 11 AF SP I IXH 11 100 101 E5 SP SP 2 PUSH IY SP 2 IYL X X 11 III 101 FD IS SP I IYH 11 100 101 E5 SP SP 2 POPqq qqH SP I X X 11 qqO 001 10 qqL SP SP SP 2 POP IX IXH SP...

Страница 100: ...r suit 01 Be 1 0 otherwise PIV 1 Zflag is 1 il A HL otherwise Z o a Bit ADD A r A A r X X V 0 lO r Arithmetic ADD A n A A n X I X V 0 II IQQQ 110 000 B and Logical 001 C 010 D Group ADD A HL A A HL X...

Страница 101: ...Y X X X V 11 101 101 ED 15 01 550 010 ADD IX pp IX IX pp X X a 11 all 101 DD 15 pp Reg 01 ppl 001 00 BC 01 DE 10 IX 11 SP ADD IY rr IY IY rr X X X II III 101 FD 15 rr Reg 00 rrl 001 00 BC 01 DE 10 IY...

Страница 102: ...II 6F II 101 101 ED 01 100 III 67 II 001 011 CB 01 b r II 001 011 CB 01 b 110 11 011 101 DD II 001 011 CB d 01 b 110 II 111 101 FD 11 001 all CB d OJ b 110 II 001 011 CB jJ b 11001011 CB jJ b 110 II 0...

Страница 103: ......

Страница 104: ...cation s is copied into the Z flag Symbolic Symbol Operation Symbol Operation Notation S Sign flag S 1 if the MSB of the result is 1 I The flag is affected according to the result of the Z Zero flag Z...

Страница 105: ...eration 10RQ is also generated concurrently with Ml during an interrupt acknowledge cycle to indi cate that an interrupt response vector can be placed on the data bus MI Machine Cycle One output activ...

Страница 106: ...be enabled onto the CPU T CLOCK Ao A15 T Tw T time or cycle and three or more T cycles make up a machine cycle Ml M2 or M3 for instance Machine cycles can be extended either by the CPU automatically i...

Страница 107: ...achine cycle NMI s falling edge must occur no later II the rising edge of the clock cycle preceding TLAST Figure 9 Non Maskable Interrupt Request Op Ion Bus Request Acknowledge Cyclo The CPU samples B...

Страница 108: ...re 9 Figure 11 Halt Acknowledge Cycle Reset Cycle RESET must be active for at least three clock cycles for the CPU to properly accept it As long as RESET remains active the address and data buses floa...

Страница 109: ...ime after Clock I 0 0 0 19 TdCr Mlf Clock t to Ml 1 Delay 130 100 80 20 TdCr M1r Clock t to Ml t Delay 130 100 80 21 TdCr RFSHf Clock t to RFSH I Delay 180 130 110 22 TdCr RFSHr Clock t to RFSH t Dela...

Страница 110: ...Clock I to Data Valid Delay 230 150 130 For clock periods other than the minimums shown in the table calculate parameters using the following expressions Calculated values above assumed TrC TfC 20 ns...

Страница 111: ...APPENDIX F FLOPPY ERROR CODE 36...

Страница 112: ...e This bit is an inverted copy of the IP input 50 BUSY When set command is in progress When reset no command is in progress STATUS FOR TYPE II AND III COMMANDS BIT NAME MEANING 57 NOT READY This bit w...

Страница 113: ...Is completed information furnished by Western 0IgItaJ Corporation Is beIieYed 10 be accurate and NIIabIe However no assumed by western Digital Corporation for Its use nor any Infrillgements of patent...

Страница 114: ...ay be incurred If the equipment must be returned a second time a neil Return Authorization Number must be issued Reuse of Return Authorization Numbers may result in delays in processing returns Effect...

Страница 115: ...should see that pulse going to ZERO voltage e If the step d is OK then you have a problem with either on of the a or b or c f check the 4MHZ clock signal going to pin 6 of the cPU 2 If there is a pro...

Страница 116: ...5V 2 Rl should be hooked to 5 3 for double sided drives there should be a jumper from j3 connector to PIO bit3 PIO 29 4 IE3 lin2 PIO 22 should goto u18 9 on some older rev boards its also going to pi...

Страница 117: ...y DMB6400 0 the SUPERQUAD ON DMB6400 SET SWITCHES AS FOLLOWS TOGLE SWITCH UP MEANS PRESS TO THE TOP DOWN Sl l DOWN Sl 2 DOWN 51 3 DOWN Sl 4 DavIN S2 1 2 4 5 UP S3 1 2 UP S4 1 4 DOWN S5 1 2 3 4 5 6 8 U...

Страница 118: ...is done by cutting the RAM Jl RM6 RFSH and FOC WAIT signals on the SUPER tuttI away from the inputs of HOLD U56 and ANDING them and tying the result to PRDY of the 5 100 bus XRDY see figure 2 Because...

Страница 119: ...12 0 Parts list...

Страница 120: ...24 I 2 22 I 745240 I U 68 U 69 I 2 23 I 74LS244 I U 8 1 1 24 I 74LS24S I U 44 U Sl I 2 25 I 74LS273 I U 17 I 1 25 I 745287 PROt l I U 49 I 1 27 1 74LS373 I U 25 U 30 I 2 28 1 74 LS37 4 I U 23 1 1 29 1...

Страница 121: ...I RM6 1 1 55 I 220 330 SIP 1 RM4 I 1 56 I 33 OHM DIP I RH8 I 1 57 I IN914 DIODE I CR2 I 1 58 I 5 1 V ZENER 1 CRl I 1 59 1 100 MF CAP I C2 I 1 60 I 1 MF CAP I I 21 61 I 4 7 MF CAP I C6 C3 C10 C27 C281...

Страница 122: ...13 Schematic diagram...

Страница 123: ...03 1 1 U51 42 1 D4 4 L 2 45 I l 9 1 0 5__ 1 1 92 1 2 B 93 I D7 _ 11 1 3 4 DI7 I D Q _ 12 1 t B __ DO I D 1 I 1 5 I D 2 3 q II 00 D 14 U44 6 89 I D 4 I i 5 LS245 15 38 I D 5__ I I 4 3 I D _ 7 13 40 D7...

Страница 124: ..._ _ 5 l L5240 15 RD SolJT 451 12 S l OUT 2 13 0 A J V V A t_ _r n A n I tiI R31 3_82 MI1IV CJ PWR 11 1 i 1 U24 I I 1_ _ p_W R 4_E B P TVAL 1 5 I B II z 3 P 5PJAL 2 PSYl JC 110 Z o PO BI 15 I _ P D B I...

Страница 125: ...a8QL B5TRt i 4 3 2 1 REVISIONS DESCRIPTION DATE APPROVED I I I 17 DI DZ 2 1 D D4 D 00 D7 MI It 1 l4 U37 HEADER 14 f M r1Ll l I U3 1 1 2__ B A U 0 A ______ j I U I o cO N a A 21 20 1 I POWEI FAIL RB RI...

Страница 126: ...f l 02 12 LS1l5 1 Lf D3 f I 4 C I e7 DRV 5R ql RE SET A tn 8151 10 GRAPHICS INC W REORDER NO 20 O 8 7 6 5 i 4 1 l U l l3 l 3 RM 1 5 ZZO 30 eo 14 5 3 7 6 s I i a tLR 3 t5 L512 1 514 U 3 Z_ J rLL A I uz...

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