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3 – Modifying the Demonstration Design Through
Script
Core1553BRM Verification Testbench
Actel has developed a Core1553BRM verification testbench to verify the core performance per the
MIL-STD-1553B specification. The testbench is coded in VHDL and includes several Core1553BRM
cores connected to a 1553 bus and backend interfaces. A procedural testbench controls the various
blocks and implements various test protocols.
The Core1553BRM verification testbench uses a command interpreter to apply high-level stimulus
to Core1553BRM. This allows you to directly set the Core1553BRM memory and registers through
command files and thus control operation of the core. You can create the script file using
Core1553BRM verification testbench and then apply it to the Core1553 development system. Refer
to the
Core1553BRM Handbook for more information.
Scripting
High-level command files created to control the core operation can be converted into log files by
the verification testbench. These log files can then be downloaded to the Core1553BRM
demonstration design to change its operation and test various scenarios. The demonstration CD
contains two files in the release\scripts\ directory: demo.txt and demo_log.txt. Demo_log.txt was
generated by the verification testbench from the command file demo.txt.
The demo_log.txt script programs one BRM as the BC and the other as RT 1, initializes the RT
memory tables, and sets up the BC to do BC-to-RT, RT-to-BC, and RT transmit vector commands. At
the conclusion of the script, BC memory values are compared to verify that the three messages
completed correctly. Demo.txt is fully annotated and shows the exact sequences of operations used
to generate the script file. Demo_log.txt is used to verify the operation of the demonstration
design.