XVME-6700A
USER
’S
MANUAL
Acromag, Inc. Tel: 248-295-0310
- 23 -
http://www.acromag.com
- 23 -
https://www.acromag.com
Lanes [0:7] connect directly to the Lower XMC Site's J15 connector.
Lanes [8:12] are muxed between the lo
wer 4 lanes of the Upper Site’s
J25
connector and the PEX8114 PCIe to PCI-X Bridge that is used to drive the PMC
bus. This mux should switch automatically to XMC when an XMC module is
installed into the Upper Site. If it does not this can be overridden with DIP
Switch
Lanes [13:16] connect to the upper 4 lanes of the Upper Site's J25 connector.
The PEG interface meets the
PCI Express Base Specification, Revision 3.0
and
supports:
•
Low Swing (low‐power/low‐voltage) and Full Swing operating
modes
•
Static lane numbering reversal
•
The Gen3 (8 GT/s) PCI Express frequency (not supported by XMC
connectors)
3.4 Platform Controller Hub (PCH)
The Intel 8 Series QM87 (Lynx Point) PCH provides extensive I/O support, as
listed below:
•
PCIe x4 (2)
–
There are two PCIe ports of x4 width. The first is
connected to the FPGA-based VME Bridge. The other is connected
to the Intel 82580EB Quad Gigabit Ethernet controller.
•
SATA II (2)
–
There are two SATA ports that operate up to 3Gb/sec
connected to the VME P2 connector.
•
SATA III (2)
–
There are two SATA ports that operate up to 6Gb/sec
connected to the Expansion Site connector for the optional
XBRD-9060.
•
Bootable on-board SSD Flash
–
40GB of soldered-down on-board
SSD Flash is standard on all units.
•
USB 2
.
0 (4)
–
There are two ports connected to the VME P2
connector and two ports connected to the front panel's 26-pin
connector that function at USB 2.0 or USB 1.1 speeds. There are an
additional two ports available on the Expansion Site connector for
the optional XBRD-9060
•
VGA
–
An analog VGA port is available, including DDC clock and
data, at either the VME P2 connector or the front panel's 26-pin
connector. Only one connection may be used at a time and should
auto switch when a monitor is plugged in to either port. Override
switches are available on SW2.
•
LPC
–
The Low Pin-count Bus is connected to both the NCT6106D
Super-I/O for serial ports and debug port 80 connections, in addition
to the AT97SC3204 (1.2) or SLB9665XT20 (2.0) TPM device.
•
SPI
–
The Serial Peripheral Interface is used for the onboard boot
flash.