AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 26 -
http://www.acromag.com
- 26 -
www.acromag.com
3.3.1 FIFO Data Loading and Unloading in 32-bit Format
The XR17V354 supports 32-bit Read and 32-bit Write transactions anywhere
in the mapped memory region (except reserved areas). In addition, to utilize
this feature fully, the device provides a separate memory location (apart
from the individual channel’s register set)
where the RX and the TX FIFO can
be read from/written to, as shown in Table 3.2. The following is an extract
from the table showing the memory locations that support 32-bit
transactions:
Channel N: (for channels 0 through 3) where M = 4N + 1.
RX FIFO: 0xM00
–
0xMFF (256 bytes)
TX FIFO: 0xM00
–
0xMFF (256 bytes)
RX FIFO + status: 0x(M+1)00
–
0x(M+2)FF (256 bytes data+256 bytes
status)
For example, the locations for channel 2 are:
RX FIFO: 0x0900
–
0x09FF (256 bytes)
TX FIFO: 0x0900
–
0x09FF (256 bytes)
RX FIFO + status: 0x0A00
–
0x0BFF (256 bytes data+256 bytes status)
Normal Rx/Tx FIFO Data Unloading/Loading at Locations 0x0100, 0x0500,
0x0900 and 0x0D00:
The RX FIFO data can be read out 32-bits at a time at memory locations
0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2) and 0x0D00
(channel 3). This operation is 4 times faster than reading the data in 256
separate 8-bit memory reads of RHR register (0x0000 for channel 0, 0x0400
for channel 1, 0x0800 for channel 2 and 0x0C00 for channel 3).
The TX FIFO data can be loaded 32-bit (4 bytes) at a time at memory
locations 0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2) and
0x0D00 (channel 3).
Special Rx FIFO Data Unloading at Locations 0x0200, 0x0600, 0x0A00 and
0x0E00:
The XR17V354 also provides the same RX FIFO data along with the LSR
status information of each byte side-by-side, at locations 0x0200 (channel
0), 0x0600 (channel 1), 0x0A00 (channel 2) and 0x0E00 (channel 3). The
Status and Data bytes must be read in 16 or 32-bit format to maintain data
integrity.
3.3.2 FIFO Data Loading/Unloading Through the UART Channel Registers, THR and RHR, in 8-Bit Format
The THR and RHR for each channel 0 to 3 are located sequentially at address
0x0000, 0x0400, 0x0800 and 0x0C00. Transmit data byte is loaded to the
THR when writing to that address and receive data is unloaded from the
