6.4 Multi-purpose inputs and outputs
70
U5303A User's Manual
6.4 Multi-purpose inputs and outputs
The multi-purpose I/O connectors may be used for any of the functions shown in the following table:
IO Connector Functions
Type
Description of signal
Mode /
Option
Notes
Inputs
Disabled
-
IO connector is disabled.
In-ToLogicDevices
-
The Pio_In input signal to the DPU user core
IO 1-Pio_In(0), IO 2-Pio_In(1).
These signals are resynchronized to the
sampling clock divided by 16 and transferred
from the Control FPGA to the DPU with a non-
deterministic clock cycle latency.
-FDK
In-AccumulationEnable
Level
This signal controls the execution of the
averaging sequence.
-AVG or -
PKD
IO 1 only
Outputs
Out-LogicDeviceDPUA
-
The Pio_Out output signal from the DPU user
core IO 2-Pio_Out(1).
These signals are transferred from the DPU to
the Control FPGA with a non-deterministic
clock cycle latency.
-FDK
Out-FPGASyncOut
Pulse
The SyncOut output signal from the DPU user
core. This signal is transferred from the DPU to
the Control FPGA with a deterministic clock
cycle latency.
-FDK
Out-100MHzRe-
ferenceClockDivBy2
Clock
The 100 MHz reference clock divided by 2 (50
MHz).
IO 1 only
Out-SamplingClockDivBy32
Clock
The sampling clock divided by 32.
IO 1 only
Out-AcquisitionActive
Level
Indicates that the acquisition is currently run-
ning.
Digitizer
mode
IO 1 & 2 only
Out-TriggerArmed
Level
Trigger is armed.
IO 1 & 2 only
Out-LowLevel
Level
Fixed 'low' level signal for debug purposes.
Out-HighLevel
Level
Fixed 'high' level signal for debug purposes.
Out-TriggerAcceptedResync
Pulse
Active when a valid trigger event has occurred.
This signal is resynchronized to the sample
clock.
Out-AccumulationActive
Level
Indicates that the accumulation is currently run-
ning.
IO 2 only.
Requires -
AVG or -
PKD option.
Out-AveragerAwg
-
Self-Trigger output.
IO 3 only.
Requires -
AVG or -
PKD option.
Table 6.4
- List of signals selectable for the programmables I/Os .
