2-2
API Confidential
No Copy/Reproduction Allowed
7277e Monitor Service Guide
1
2
3
VI
VO
GND
+
+
GND
HPLL2
HSMOD
FOCUS
SGND
VSMOD
ASCOR
SDA
SCL
HUNLOCK
VCC
i.c.
BDRV
HFLB
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLBL
HSYNC
VSYNC
VOUT1
VOUT2
EWDRV
VAGC
VCAP
VREF
HPLL1
HBUF
HREF
HCAP
HDRV
BIN
BSENS
BOP
XRAY
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+
+
+
+
R235
D208
R219
VR201
D206
IC203
C221
R238
C222
R259
C206
C202
C210
IC201
Q207
D201
R260
R208
R204
R220
R211
R202
R201
R213
R209
R210
R261
D207
R206
R205
R207
R218
R217
R216
R215
R214
R257
R212
R258
C203
C201
C204
C211
C208
C209
C207
C226
R251
2.2K
1N4148
1%
56.2K
100K
HVADJ
1N4148
LM7812
16V
100U
(EL)
43K
50V
0.22U
(EL)
1%
25.5K
100V
0.18U
(PE)
2%
100V
2200P
(EPI)
2%
100V
O.01U
(EPI)
TDA4854
H945
1N4148
1%
21.5K
680K
2K
36K
510
100
100
3.3K
100
100
68K
1N4148
10K
130K
12K
20K
(1%)
100K
(1%)
16K
(1%)
2.55K
(1%)
1.27K
(1%)
3.6K
22K
(1%)
200K
50V
47U
(EL)
25V
47OU
(EL)
50V
1U
(EL)
100V
2200P
(PE)
100V
0.1U
(PE)
100V
8200P
(PE)
100V
0.1U
(PE)
25V
100U
(EL)
2K
+12V
+12V
SCL
H-SYNC
V-SYNC
SC0
SDA
SC1
BLANK
+6.5V
HDRV
EWDRV
SC2
V2
V1
HFLB
FOCUS
VSMOD
HSMOD
+48V
+48V
CLAMP
+14V
TP3
TP2
Fig 2 Autosync Deflection Controller circuit
2.1.3 H-Driver & Output CKT
HDRV signal comes from IC201 pin8, then goes into Q301, Q301 constitutes an inverting stage and
combines with T302 to drive Q302. Q302, C306,C309, D305 constitute the H-output CKT with diode
modulator mode.
2
3
1
6
5
4
3
1
+
R372
R384
Q302
D305
T302
C305
Q301
C308
C307
C302
C301
C309
D303
D304
D302
D301
C306
C303
R305
R303
R304
L308
R301
R375
C304
FR306
FR374
FR373
C331
R307
Q320
1/4W
47K
1/4W
100
BU2520AF
FMP-2FU
19.20079.011
50V
0.047U
(PE)
C2235
(D)
1KV
680P
(D)
2KV
100P
(D)
50V
220P
50V
1U
(EL)
1.6KV
6200P
(PP)
1N4148
1N4005
1N5818
1N4148
630V
4300P
(PP)
50V
0.1U
(MONO)
1/4W
33
1K
1W
0.22
(SHORT)
3W
220
4.7K
(MPE)
100V
0.22U
1/4W
1
1/4W
27K
1/4W
3.9K
(D)
500V
680P
1/4W
10K
H945
HFLB
DYH+
HDRV
+5V
+45V
HBNK
Fig 3 HDRV & output circuit
2.1.4 Dynamic Focus CKT
Содержание 7277e
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