Manual PCI-WDG-CSM
27
1st Read:
Status byte
2nd Read:
Low byte of latched data
3rd Read:
High byte of latched data.
After any latching operation of a counter, the contents of its hold register must be read before any
subsequent latches of that counter will have any effect. If a status latch command is issued before the
hold register is read, then the first read will read the status, not the latched value.
