Abov MC96F6332D, Руководство пользователя

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MC96F6432
206 June 22, 2018 Ver. 2.9
11.12.11 USI0 SPI Mode
The USI0 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following
features.
- Full Duplex, Three-wire synchronous data transfer
- Mater and Slave Operation
- Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3)
- Selectable LSB first or MSB first data transfer
- Double buffered transmit and receive
- Programmable transmit bit rate
When SPI mode is enabled (USI0MS[1:0]=
”11”), the slave select (SS0) pin becomes active LOW input in slave
mode operation, or can be output in master mode operation if USI0SSEN bit is set to
‘0’.
Note that during SPI mode of operation, the pin RXD0 is renamed as MISO0 and TXD0 is renamed as MOSI0
for compatibility to other SPI devices.
11.12.12 USI0 SPI Clock Formats and Timing
To accommodate a wide variety if synchronous serial peripherals from different manufacturers, the USI0 has a
clock polarity bit (CPOL0) and a clock phase control bit (CPHA0) to select one of four clock formats for data
transfers. CPOL0 selectively insert an inverter in series with the clock. CPHA0 chooses between two different
clock phase relationships between the clock and data. Note that CPHA0 and CPOL0 bits in USI0CR1 register
have different meanings according to the USI0MS[1:0] bits which decides the operating mode of USI0.
Table below shows four combinations of CPOL0 and CPHA0 for SPI mode 0, 1, 2, and 3.
Table 11-20 CPOL0 Functionality
SPI Mode CPOL0 CPHA0 Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
1 0 1 Setup (Rising) Sample (Falling)
2 1 0 Sample (Falling) Setup (Rising)
3 1 1 Setup (Falling) Sample (Rising)