4.6
Configurable logic blocks
IP11009-1 v4
4.6.1
Application
GUID-F5D6F065-441B-4296-AC56-F4DC1F5487E3 v3
A set of standard logic blocks, like AND, OR etc, and timers are available for adapting the IED
configuration to the specific application needs.
4.6.2
Setting guidelines
GUID-E6BD982D-9E47-4CC2-9666-6E5CABA414C0 v4
There are no settings for AND gates, OR gates, inverters or XOR gates.
For normal On/Off delay and pulse timers the time delays and pulse lengths are set from the
PST tool.
Both timers in the same logic block (the one delayed on pick-up and the one delayed on drop-
out) always have a common setting value.
For controllable gates, settable timers and SR flip-flops with memory, the setting parameters
are accessible via the PST tool.
4.6.2.1
Configuration
GUID-D93E383C-1655-46A3-A540-657141F77CF0 v4
Logic is configured using the ACT configuration tool in PCM600.
Execution of functions as defined by the configurable logic blocks runs according to a fixed
sequence with different cycle times.
For each cycle time, the function block is given an serial execution number. This is shown when
using the ACT configuration tool with the designation of the function block and the cycle time,
see example below.
IEC09000695_2_en.vsd
IEC09000695 V2 EN-US
Figure 6:
Example designation, serial execution number and cycle time for logic
function
The execution of different function blocks within the same cycle is determined by the order of
their serial execution numbers. Always remember this when connecting two or more logical
function blocks in series.
Always be careful when connecting function blocks with a fast cycle time to
function blocks with a slow cycle time.
Remember to design the logic circuits carefully and always check the execution
sequence for different functions. In other cases, additional time delays must be
introduced into the logic schemes to prevent errors, for example, race between
functions.
1MRK 511 445-UEN B
Section 4
Logic
Switchgear control unit SAM600-IO
33
Application manual
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