ABB Relion REQ650, Руководство по применению

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IEC09000695_2_en.vsd
IEC09000695 V2 EN
Figure 101: Example designation, serial execution number and cycle time for
logic function
The execution of different function blocks within the same cycle is determined by the
order of their serial execution numbers. Always remember this when connecting two
or more logical function blocks in series.
Always be careful when connecting function blocks with a fast cycle
time to function blocks with a slow cycle time.
Remember to design the logic circuits carefully and always check the
execution sequence for different functions. In other cases, additional
time delays must be introduced into the logic schemes to prevent
errors, for example, race between functions.
Default value on all four inputs of the AND gate are logical 1 which
makes it possible for the user to just use the required number of inputs
and leave the rest un-connected. The output OUT has a default value
0 initially, which will suppress one cycle pulse if the function has been
put in the wrong execution order.
11.5 Fixed signals FXDSIGN
11.5.1 Identification
Function description IEC 61850
identification
IEC 60617
identification
ANSI/IEEE C37.2
device number
Fixed signals FXDSIGN - -
11.5.2 Application
The Fixed signals function FXDSIGN generates nine pre-set (fixed) signals that can
be used in the configuration of an IED, either for forcing the unused inputs in other
function blocks to a certain level/value, or for creating certain logic. Boolean, integer,
floating point, string types of signals are available.
1MRK 505 291-UEN A
Section 11
Logic
253
Application manual