Publication No.
500-9300007876-000
Rev. C.0
Functional Description 75
Serial Interfaces
The serial interfaces are provided by the Lattice FPGA. The XVR16
ʹ
s serial ports
are fully compatible with the 16550D UART. Each serial interface provides a
16 byte FIFO, offering higher performance than earlier used standard serial
interfaces. The UARTs have programmable baud rate generators capable of up to
115200 baud. There are four address locations defined for serial interfaces on
standard PCs. The serial interfaces are I/O mapped and can occupy four address
ranges.
• COM1 and COM2 are available out the rear P2
• COM3 is RS232 only interface located on the Front Panel
• COM4 is a transistor-transistor logic (TTL) serial port supporting
communication with the BMC
Watchdog Timer
The XVR16 provides a Watchdog timer (WDT) in the onboard FPGA. This timer
can be loaded with 8 different count values ranging from 2 ms up to 67 s. Once
loaded and enabled, the WDT will count until the load value is reached, or the
count is reset by accessing the WDT Keep Alive Register. If the Keep Alive
Register is not accessed before the count is reached, the WDT will reset the
XVR16. See
Watchdog Timer (WDT) Refresh (0x60D)
MRAM
The MRAM is a 512 KByte Non-volatile memory residing at location 0xFC000000
memory space. The total 512 KByte space is addressed with eight 64 KByte
memory pages. Memory page selection is controlled by the MRAM register
located at IO Space 0x68A. See
for additional details on MRAM Page
Registers.
Timers
The XVR16 FPGA provides two 32-bit timers with load, continuous and one-shot
modes, and interrupt capability. See
and
GPIO (0-11)
The GPIO is sourced from the FPGA. Twelve GPIO pins are available on the VME
connector P2 (P7302). These pins can be used for I/O functions with output 3.3 V
signals as well as GPIOs are 3.3 V only and are not 5 V tolerant inputs. GPIO (0..9)
can be used only when the DVI1 is not installed. GPIO (0..9) and DVI1 are
mutually exclusive ordering options. GPIO (10..11) are always available. Refer to
for more GPIO details.
Board
Configuration
The XVR16 FPGA provides registers dedicated to providing information
regarding the unit options for items such as Front panel presence, number and
type of video displays, Ethernet ports, SATA ports, USB ports, etc.
for more register descriptions that include board
configuration registers.
6.17.2 Temperature Sensors
Temperature sensors are integrated in the CPU die, PCH die, and the sensor of the
FPGA that displays the local onboard temperature of the XVR16 and is located
beneath the CPU heat sink.
The BMC or FPGA sensor provides an integrated over-temperature output that
can be used to take actions such as reducing the CPU speed.
The die sensors of the CPU and PCH may be programmed to take actions to
protect the devices from overheating. The CPU temperature sensor has a