70 XVR16*4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer
Publication No.
500-9300007876-000
Rev. C.0
Overlapping Slave DTACK response and System Controller BERR:
The
VMEbus specification allows the System Controller (or BERR Timer) to generate a
VME Bus Error (BERR) without looking at the status of the VMEbus DTACK
signal. When these VMEbus signals occur simultaneously (or /-15 ns) in
response to a local processor generated read cycle that initiates a Tsi148 Master
VMEbus read cycle, then the PCI delayed read retry that happens as part of this
Tsi148 VME read transaction may hang in retry and never return data to the
processor from either the completed read cycle (DTACK) or the BERR.
The user can ensure that this is not a system issue by using either of the following:
1. Always ensure that the BERR timeout of the VME System Controller is set to
longer (at least 10
S) than the maximum Slave DTACK response time.
2. If the user cannot ensure that the BERR timeout is longer than the maximum
Slave DTACK response time, then the user should use the Tsi148 DMA
controller to initiate VME read access, instead of the processor initiating the
VME read access.
6.7.3 VME \SYSRESET Direction
The XVR16 provides a non-volatile UEFI setup screen of the VME \SYSRESET
direction. In the setup screen the user can decide whether the XVR16 can drive the
VME \SYSRESET and also decide whether the VME \SYSRESET should be used
as an input.
6.8 Interrupt Controller
The Mobile Intel QM87 Express Chipset provides an ISA compatible
Programmable Interrupt Controller (PIC) that consists of two 82C59A devices
with eight interrupt request lines each. The two controllers are cascaded so that
fourteen external and two internal interrupt sources are available. The master
interrupt controller provides IRQ [7...1]; the slave interrupt controller provides
IRQ [15...8]. IRQ2 is used to cascade the two controllers, IRQ0 is used as a system
timer interrupt and is tied to interval timer 1, counter 0. The remaining fourteen
interrupt lines are mapped to various onboard devices. Each 82C59A provides
several internal registers. The interrupts on the IRQ input lines are handled by
two registers: the interrupt request register IRR and the in-service register ISR.
For programming details see the 82C59A data sheet.
The XVR16 also supports the Interrupt handling of the Advanced Programmable
Interrupt Controller (APIC). This handling of the APIC interrupt services must be
supported by the operating system. The I/O APIC handles interrupts very
differently than the 8259.
6.9 Timer (8254)
The XVR16 is equipped with an 8254 compatible timer. This timer contains three
counters. Each counter output provides a key system function. Counter 0 is
connected to interrupt controller input IRQ0 and provides a system timer
interrupt for time-of-day, floppy disk time-out and other system timing functions.
Counter 1 generates a refresh request signal and Counter 2 generates the sound
for the speaker.