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54 XVR16*4th Generation Intel® Core™ i7 Based Rugged VME Single Board Computer Publication No. 500-9300007876-000 Rev. C.0
5.3.6 XMC1 Connector (J15)
The following tables list the pin assignments of the onboard XMC1 connectors.
The XMC1 slot provides an x8 lane wide PCI Express interface. Only if an XMC
mezzanine board is installed are the PCI express lanes muxed to the XMC slot;
otherwise, these lanes are muxed to the PMC1 bridge.
The XMC1 Connectors J15 and J16 are electrically and mechanically compliant to
the specification VITA 42.0 and IEEE 1386.1.
Figure 5-18 XMC Connector J15 and J16
A1 A19
F19
F1
Table 5-16 XMC1 Connector Pin Assignments (J15)
Pin Row A Row B Row C Row D Row E Row F
1 TX0+ TX0- +3.3 V TX1 TX1- +5 V
2 GND GND TRST GND GND
XMCRSTIN
a
3 TX2+ TX2- +3.3 V TX3+ TX3- +5 V
4 GND GND TCK GND GND
XMC1_RSTOUT
b
5 TX4+ TX4- +3.3 V TX5+ TX5- +5 V
6 GND GND TMS GND GND +12 V
7 TX6+ TX6- +3.3 V TX7+ TX7- +5 V
8 GND GND TDI GND GND -12 V
9 NC NC RPS NC NC +5 V
10 GND GND TDO GND GND GA0
11 RX0+ RX0- MBIST RX1+ RX1- +5 V
12 GND GND GA1 GND GND XMC1PRESENT
13 RX2+ RX2- +3.3 V AUX RX3+ RX3- +5 V
14 GND GND GA2 GND GND BMC_SDA
15 RX4+ RX4- RPS RX5+ RX5- +5 V
16 GND GND MVMRO GND GND BMC_SCL
17 RX6+ RX6- RFU RX7+ RX7- RFU
18 GND GND RPS GND GND RPS
19 CLK+ CLK- RPS WAKE ROOT RPS
a
Reset driven by XVR16
b
Reset driven by Mezzanine