Publication No. 500-9300527837-000 Rev. A.0
FPGA Registers 79
6.66 Test Register (0x6C7)
6.67 Backplane Status Register (0x6CA)
This register inverts the Geographic Addressing (GA) bits so that software can
read a true slot number, e.g., the SBC347A in slot 1 (only GA0 pulled low) results
in bits 4 to 0 reading 00001
b
.
6.68 SSD Status Register (0x6CB)
SSD write protection is set by the
Bits
Description
Default
7 to 1
Reserved
0000000
b
0
CPU daisy-chain status:
1 = Chain fault
0 = Chain OK
N/A
Bits
Description
Default
7
SYSCON status:
1 = SBC347A is fitted into a System Controller slot (SYSCON backplane pin is low)
0 = SBC347A is not fitted into a system controller slot (SYSCON backplane pin not pulled low)
N/A
6
NVMRO status:
1 = Backplane NVMRO signal is asserted
0 = Backplane NVMRO signal is negated
N/A
5
VPX GAP pin status:
1 = GAP pin is high
0 = GAP pin is low
N/A
4 to 0
VPX GA4 to GA0 status (inverted)
N/A
Bits
Description
Default
7 to 1
SSD7 to SSD1 write protect status:
SSD7 to SSD1 are not supported
0000000
b
0
SSD0 write protect status:
0 = SSD0 is write protected
1 = SSD0 is not write protected
N/A