Publication No. SBC329-HRM/1
Functional Description 53
5.4.2
REFCLK
pins E8 and F8 can be optionally
configured as a PCIe Gen3 compliant 100 MHz REFCLK signal. This can be
connected to other boards in the backplane that are part of the PCIe bus segment.
The SBC329 can also receive VPX REFCLK as a PCIe REFCLK signal, and use it to
clock the backplane facing PCIe Non-Transparent ports for when the SBC329 is used
as part of a peer-to-peer system.
Control of the VPX REFCLK signal is provided by the EEPROM DIP switch, which is
accessible through the BIOS setup menus. Using these settings, it is possible to set
the clock to be an input, output or disabled.
NOTE
Use of the VPX REFCLK as a 100 MHz PCIe REFCLK input may require the PCIe switch
configuration EEPROM to be set up accordingly.
5.4.3
Module Maskable Reset
OpenVPX supports a second reset input from the backplane (
), which
may be masked under software control.
The SBC329 is hard reset when the Maskable Reset backplane signal is asserted for
more than 10 µS, unless masked by software in the FPGA. The reset is not masked by
default.
The SBC329 is also able to drive the Maskable Reset under software control via the
FPGA, for example to reset a subset of other boards in the system.
5.4.4
Global Discrete
OpenVPX supports a single open-drain GPIO signal, GDISC1 (
), which is
bused to all module slots in the backplane. Its function is not defined by the
specification, but it could be used to provide a common control or status function to
all boards in the system.
The SBC329 treats the GDISC1 pin as a GPIO pin, and the FPGA provides registers to
drive the pin, to read its status and to generate an interrupt in the same way as the
other GPIO signals.
