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LogiCORE™ IP
CAN v3.2

Getting Started Guide

UG186 April 19, 2010

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Summary of Contents for LogiCORE IP CAN 3.2

Page 1: ...LogiCORE IP CAN v3 2 Getting Started Guide UG186 April 19 2010...

Page 2: ...ed or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx 2005 2010 Xilinx Inc XI...

Page 3: ...Feedback 10 Core 10 Document 10 Chapter 2 Licensing the Core Before you Begin 11 License Options 11 Simulation Only 11 Full System Hardware Evaluation 11 Full 12 Obtaining Your License Key 12 Simulati...

Page 4: ...sign 19 component_name doc 19 component_name implement 20 component_name implement results 20 component_name simulation 20 component_name simulation functional 21 simulation timing 22 Implementation S...

Page 5: ...Introduction Chapter 2 Licensing the Core Chapter 3 Quick Start Example Design Figure 3 1 Example Design 13 Figure 3 2 CAN Main Screen 14 Chapter 4 Detailed Example Design Figure 4 1 Example Design Co...

Page 6: ...6 www xilinx com CAN Getting Started Guide UG186 April 19 2010...

Page 7: ...nx Chapter 2 Licensing the Core provides information about licensing the core Chapter 3 Quick Start Example Design provides instructions to quickly generate the core and run the example design through...

Page 8: ...items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Angle brackets User defined variable or in code samples directory name Verti...

Page 9: ...support and submitting feedback to Xilinx About the Core The CAN core is a Xilinx CORE Generator IP core included in the latest IP Update on the Xilinx IP Center For detailed information about the cor...

Page 10: ...dates to this document are also available at the CAN product page Technical Support For technical support visit www support xilinx com Questions are routed to a team of engineers with expertise using...

Page 11: ...nse key is provided with the Xilinx CORE Generator tool This key lets you assess core functionality with either the example design provided with the CAN core or alongside your own design and demonstra...

Page 12: ...ilinx CORE Generator software Full System Hardware Evaluation License To obtain a Full System Hardware Evaluation license do the following 1 Navigate to the CAN product page for this core 2 Click Eval...

Page 13: ...Example Design Overview Figure 3 1 illustrates the CAN example design The CAN example design consists of the following CAN netlist HDL wrapper which instantiates the CAN netlist Customizeable demonst...

Page 14: ...oject 3 Type a directory name This example uses the directory name design 4 Do the following to set project options Part Options From Target Architecture select the desired family For a list of suppor...

Page 15: ...For Windows ms dos cd proj_dir quickstart implement ms dos implement bat For Linux Linux shell cd proj_dir quickstart implement Linux shell implement sh These commands execute a script that synthesiz...

Page 16: ...e simulation transcript and the waveform Timing Simulation Timing simulation is supported only for the Full System Hardware Evaluation and Full license types as the core cannot be implemented using a...

Page 17: ...ch top directory link white text invisible project directory topdirectory Top level project directory name is user defined project_directory component name Core release notes file component_name doc P...

Page 18: ...with the core which may include last minute changes and updates Table 4 1 Project Directory Name Description project_dir component_name ngc Top level netlist component_name v hd Verilog or VHDL simul...

Page 19: ..._dir component_name example_design component_name _top ucf Provides example constraints necessary for processing the CAN core using the Xilinx implementation tools component_name _top v hd The VHDL or...

Page 20: ...bat sh A Windows bat or Linux script that processes the example design xst prj The XST project file for the example design that lists all of the source files to be synthesized Only available when the...

Page 21: ...and runs the simulation simulate_ncsim sh A macro file for Cadence IES that compiles the HDL sources and runs the simulation in a Linux environment simulate_ncsim bat A macro file for Cadence IES tha...

Page 22: ...ion simulate_ncsim sh A macro file for Cadence IES that compiles the post par timing netlist demonstration test bench files and runs the simulation in a Linux environment simulate_ncsim bat A macro fi...

Page 23: ...et device Performs static timing analysis on the routed design using Timing Analyzer TRCE Generates a bitstream Enables Netgen to run on the routed design to generate a VHDL or Verilog netlist as appr...

Page 24: ...t bench Starts a simulation of the test bench Opens a Wave window and adds signals of interest wave_mti do wave_ncsim sv Runs the simulation to completion Example Design Configuration Figure 4 1 illus...

Page 25: ...signals are generated A reset is applied to the example design The Baud Rate Prescalar register and Bit Timing registers are written to These registers are read from and the values read are compared w...

Page 26: ...le interrupts for TXBFLL and RXOK bits This register is read from and the value read is compared with the value written Acceptance Filter ID Register 1 and Acceptance Filter Mask Register 1 are writte...

Page 27: ...d for individual system requirements Changing the Data You can change the contents of the message written to the TX FIFO TX HPB by changing the procedure call that writes to the TX FIFO and the TX HPB...

Page 28: ...28 www xilinx com CAN Getting Started Guide UG186 April 19 2010 Chapter 4 Detailed Example Design...

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