Xerox CX PRINT SERVER 560 Reference Manual Download

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Summary of Contents for CX PRINT SERVER 560

Page 1: ...Xerox 560 Computer Reference Manual 90 30 76A...

Page 2: ...oration 701 South Aviation Boulevard lEI Segundo California 90245 _213679 4511 1974 Xerox Corporation XEROX Xerox 560 Computer Reierence iVianuai FIRST EDITION 90 30 76A January 1974 Price 7 25 Printe...

Page 3: ...Symbol LN OPS Reference Manua I 90 09 52 Xerox Macro Symbol LN OPS Reference Manual 90 1578 Manual Content Codes BP batch processing LN language OPS operations RP remote processing RT real time SM sys...

Page 4: ...Digit and Sign Detection 81 Virtual and Real Memory 17 Overflow Detection 82 Types of Addressing 19 Decimal Instruction Nomenclature 82 Memory Address Control 26 Condition Code Settings 82 Program St...

Page 5: ...m Control Panel 161 Operating Procedures and Information ___ 164 12 Typical 28 Word Portion of Memory Stack for PSS and PLS 102 6 SYSTEM CONFIGURATION CONTROL 167 13 Formats of I o Instructions 128 Co...

Page 6: ...24 Control Word Register Q30 X 1 E ___ 165 13 Description of I o Instructions 128 24 Bit Assignments Address Compare Register Q31 X 1F 166 14 I o Status Information Register R 130 25 Functions of Proc...

Page 7: ...checking is performed on each byte of information for most system interfaces and internal control signals Most fai led instructions are automatically retried and uninter rupted processing continues Th...

Page 8: ...tics Full parity checking on all data and addresses communicated in either direction on buses between memory units and processors providing fault de tection and location capability to permit the opera...

Page 9: ...h to the computer center via common carrier lines and local terminals directly STANDARD AND OPTIONAL FEATURES A basic system has the following standard features A basic processor BP that includes Full...

Page 10: ...o generalized conversion in structions provide for bidirectional conversions between internal binary and any other weighted number system including BCD 4 Time Sharing Features Call Instructions These...

Page 11: ...one unit to another in the event of a failure with no loss of functional capability only capacity In addi tion a nonworking subset of the total system may be logically isolated partitioned so that ma...

Page 12: ...multiple capa bility makes the system particularly effective in multi use applications The major multiuse features are described in the follow ing paragraphs 6 Multiuse Features Multiprocessor Featur...

Page 13: ...systems This function provides these basic features 1 Control of the External Direct Input Output bus Ex ternal DIO used for controlling system maintenance and special purpose units such as analog to...

Page 14: ...eripheral devices The MIOP com municates with device controllers via the I o bus which connects to the Controller Interface CI SYSTEM CONTROL PROCESSOR The System Control Processor performs these prim...

Page 15: ...Interface r ____I I I rocessoq BUS 1fT T 2 1 System I Control I Processor I L_ _J r 1 System I I Control I LC o J External Interrupts Basic Processor MIOP I I u I I I I I I I I I Remote Terminal Conso...

Page 16: ...eral Register Designator 8 11 ITIJ Index Register Designator 12 14 Reference Address Field 111111111 11111111 III 15 31 Memory 1 31 digit Decimal Accumu lator Reserved PROGRAM STATUS WORDS OJ Conditio...

Page 17: ...ram into actual addresses as seen by the memory system Thus when the memory map is in effect any program can be broken into 512 word pages and dy namically relocated throughout memory in whatever page...

Page 18: ...ident operating system MAPPED MODE Although the memory map is located in the Memory Inter face MI it functions as part of the basic processor The basic processor communicates with memory through the M...

Page 19: ...ad dressing is performed only if this bit position con tains a one Operation code This 7 bit field contains the code that designates the operation to be performed See the inside front and back covers...

Page 20: ...hapter 6 together with a two position switch that selects one of two 14 Main Memory possible clock and power sources Memory units may con tain two four or six ports which have a fixed priority order f...

Page 21: ...P P P P P P P P P P P P P P P P 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 Memory Bus 1 Memory Bus 2 I 1 I I 1 I I Memory L Memory I TntArfnC A I Interface I I I I I Basic f I I Processor I I RM...

Page 22: ...sor i e basic processor RMP or MIOP can gain 16 Main Memory access to a given memory location without encountering interference from another processor that is making sequen tia I requests Two memory u...

Page 23: ...ions See also Figure 5 which illustrates the control and data flow during address generation 1 Instruction Address This is the address of the next instruction to be executed For real real extended and...

Page 24: ...ress If write operation trap on write protect violation Figure 5 Addressing Logic Fetch contents of register Add 20 22 bit index to 17 bit direct reference address or 20 bit indirect reference address...

Page 25: ...address is defined as the final virtual address computed for an instruction Note however that some instructions do not use the effective address as a location reference instead the effective address...

Page 26: ...tion register that initially contains zeros in the two low order bit positions 32 and 33 The displacement value from the index register is then aligned with the instruction register as an integer acco...

Page 27: ...d for incrementing at the halfword address level The final effective virtual address is formed by the address gen erator and if the value of the reference address is greater than 15 the effective virt...

Page 28: ...operation indexing alignment Effective virtual address The 8 high order bits of the effective address are replaced with ll bit page address N from memory map Final memory address which is the actual...

Page 29: ...the index register contents If the instruction specifies indirect addressing bit position 0 contains one the 17 bit reference address is used to ac cess an indirect word in memory The low order 20 bi...

Page 30: ...Ir o 1 2 3 4 6 I 2 f 2 3 1 4 5 2 1 8 9 o lo0 Figure 9 Generation of Effective Virtual Address Indirect Real Extended Addressing These are the register formats for byte string instructions Byte string...

Page 31: ...upt location is not an interrupt instruction if it is executed as the result of a program branch to the interrupt location under normal program control The only va Iid interrupt instructions are XPSD...

Page 32: ...he 20 bit reference address as a rea I address except counter 4 with out indexing or mapping Interrupt Counter 4 uses the map if mapping is called for Access protect and write lock violations are not...

Page 33: ...effect whenever the memory map is in effect PSWs 9 1 and the basic processor is operating in the slave mode PSWs 8 1 or in the master protected mode PSWs 61 1 Access protection is not in effect when t...

Page 34: ...y page is unlocked write access to that page is permitted independent of the key value 28 Main Memory 2 A key value of 0000 is a skeleton II key that will open any lock thus write access to any memory...

Page 35: ...urrent floating point mode controls by executing the STCF instruction Designation Function MS Master slave mode control The basic pro cessor is in the master mode when this bit and the mode altered bi...

Page 36: ...ntralized Interrupts When all the conditions for acknowledging the interrupt have been achieved the basic processor stops executing the current program and executes the instruction in the cor respondi...

Page 37: ...ey are disabled inhibited or both disabled and inhibited Generally if the enable disable flip flop is off level is disabled the interrupt level can undergo all state changes except that of moving from...

Page 38: ...sor is a member When the processor bus becomes avai lable and the basic processor is ut un interruptible point the in terrupt system transmits the interrupt address to the basic processor It initiate...

Page 39: ...3 EI 3 21 Override 118 76 first 12 levels 22 119 77 23 120 78 24 121 79 25 122 7A 26 123 7B 27 88 58 Counter 1 zero 22 Counter 89 59 Counter 2 zero CI 0 23 Equals Zero 90 5A Counter 3 zero 24 91 5B C...

Page 40: ...or a PSS instruction The processor fault interrupt level is triggered by a signal when certain fault conditions are detected A POLR instruction must be used to reset the fault The memory fault interr...

Page 41: ...group is disabled removed from the interrupt recognition priority chain Consequently a waiting enabled interrupt level in an inhibited group does not prevent a lower priority waiting enabled interrup...

Page 42: ...m The execution of a modify and test instruction in an interrupt location automatically clears and arms the corresponding in terrupt level allowing the interrupted program to continue When a modify an...

Page 43: ...DH trap occurs after completion of instruction For DW and DH instruc tion is aborted with memory register CC1 CC3 and CC4 unchanged 68 44 Floating point arithme At detection tic fault 1 Characteristic...

Page 44: ...tec TCC1 2 3 0 tion the PDFt flag wi II be set TCC4 0 if parity error on genera I reg ister or internal con trol register TCC4 1 if other hardware errors 77 4D Instruction exception None The PDF t fla...

Page 45: ...includes immediate operand instructions that specify indirect addressing a one in bit 0 of the instruction If a nonexistent instruction is detected the basic processor traps to location X1401when the...

Page 46: ...slave mode or master protected mode using the mem ory map When memory protection violation occurs the basic processor aborts execution of the current instruction 40 Trap System without changing prote...

Page 47: ...the new PSWs The condition code and instruc tion address portions of the PSWs remain at the va lue loaded from memory FIXED POINT OVERFLOW TRAP Overflow can occur for any of the following instruction...

Page 48: ...LAD ttA hyphen indicates that the condition code bits are not af fected by the condition given under the Meaning ll heading 42 Trap System If none of the above conditions occurred but charac teristic...

Page 49: ...CAL2 X 4A for CAL3 or X 4B for CAL4 Execution of the XPSD or PSS instruction in the trap location is as follows 1 Store the current PSWs The stored condition code bits are those that existed prior to...

Page 50: ...ubleword and byte string instructions that yield an unpredictable result when an incorrect register is specified this type of fault is called invalid register designation II and in cludes the followin...

Page 51: ...ubsequent inputs Traps caused by conditions detected during operand fetch and store memory cycles such as nonexistent memory ac cess protection violation and memory parity error mayor may not leave re...

Page 52: ...ed before altering registers CCl 4 may be changed but not used as input to any of these instructions XPSD LPSD PSS PLS If a trap occurs due to storing the old PSWs or fetching the new PSWs the instruc...

Page 53: ...ress any doubleword in main memory or in the current block of general registers The addressed doubleword is auto matically located within doubleword storage boundaries The low order bit of the referen...

Page 54: ...ution of the instruction this field is used to modify the source address of an operand the destination ad dress of a result or both 48 Instruction Repertoire h Reserved fields In any format diagram th...

Page 55: ...or more ex amples to i ustrate the results of the instruction These examples are intended only to show how the in structions operate and not to demonstrate their full capabi lity Within the examples...

Page 56: ...e instruction LI LOAD IMMEDIATE Immedi ate operand LOAD IMMEDIATE extends the sign of the value field bit position 12 of the instruction word 12 bit positions to the left and then loads the 32 bit res...

Page 57: ...789ABCDEF R xxxxxxxx X 012345671 CC xxxx xx10 Example 3 odd Rfield value Before execution After execution ED X100000000123456781 XI00000000123456781 R xxxxxxxx XI00000000I CC xxxx xx10 LCH LOAD COMPLE...

Page 58: ...the fixed point arithmetic trap mask AM is a 1 the BP traps to location X 43 after execution of LOAD ABSOLUTE WORD otherwise the BP executes the next instruction in sequence LCD LOAD COMPLEMENT DOUBL...

Page 59: ...and CC2 is set to 1 otherwise CC2 is reset to O Affected R Ru 1 CC2 CC3 CC4 Trap Fixed point overflow IED1 32 _ 63 Ru1i IEDI 0 _ 31 R Condition code settings 2 3 4 Absolute value of effective doublew...

Page 60: ...isters the set of words to be loaded begins with the word pointed to by the effective address of LM and the set of registers begins with register R The set of registers is treated modulo 16 i e the ne...

Page 61: ...ound FR floating significance FS floating zero FZ and floating normalize FN mode control bits respectively however if bit 11 is 0 the FR FS FZ and FN control bits are not affected The functions of the...

Page 62: ...alignment After execution X 89ABCDEF XI 89ABCDEF89ABCDEF Register Rul contains a 32 bit mask If R is an even value STORE SELECTIVE stores the contents of register R into the effective word location in...

Page 63: ...trol bits of the program status words into the effective byte location as fo lIows Affected EBL PSWs 0_7 EBL ANALYZEjlNTERPRET INSTRUCTIONS ANLZ ANALYZE Word index alignment ANALYZE evaluates the effe...

Page 64: ...ing is always per formed with an index register in the current register block if bits 12 14 of the analyzed instruction are nonzero During rcc extended cddrcs5ing the effec tive virtual address of the...

Page 65: ...ting shown in Table 6 should be increased by 2 Affected R CC r ___ 1 L _ ____1 ___ 1 1 __ _ VIIUIIIUIi vuc ClllIll I 2 3 4 Instruction addressing type 0 0 0 Byte 0 0 Immediate byte 0 0 Halfword 0 0 Wo...

Page 66: ...for an add or subtract instruction there ves no carrl of a l bit cut of the h gh order sign bit position of the result Carry for an add or subtract instruction there was a l bit carry out of the sign...

Page 67: ...effective doubleword to the contents of registers Rand Ru 1 treated as a single 64 bit register loads the 32 low order bits of the sum into reg ister Rul and then loads the 32 high order bits of the...

Page 68: ...R o Positive 0 No fixed point overflow Fixed point overflow o No carry from bit position 0 Carry from bit position 0 If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the BP traps...

Page 69: ...f operation code decoding and traps to location X 40 with the contents of register R register Ru1 and the condition code un changed otherwise the BP executes the next instruction in sequence Example 1...

Page 70: ...o Positive quotient no overflow Fixed point overflow If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the BP traps to location X 43 with the con tents of register R CC1 CC3 and C...

Page 71: ...ccording to the value of the resultant byte This process allows modification of a byte by any number in the range 8 through 7 followed by a test If the value of the R field is zero the effective byte...

Page 72: ...y unit containing the effective location is reserved not accessi ble to other processors unti I the instruction is completed 66 Comparison Instructions of the Rfield This word is added to the effectiv...

Page 73: ...ed as a nonexistent instruction in which case the basic processor uncondi tionally aborts execution of the instruction at the time of operation code decoding and then traps to location X 40 with the c...

Page 74: ...Comparison 0 0 Equal 0 Register doubleword less than effective doub Ieword o Register doubleword greater than effective doubleword CS COMPARE SELECTIVE COMPARE SE LECTIVE compares the contents of regi...

Page 75: ...ONS All logical operations are performed bit by corresponding bit between two operands one operand is in register Rand the other operand is the effective word The result of the logical operation is lo...

Page 76: ...e address does not reference memory Bit positions 15 20 and 24 of the effective virtual address are ignored Bit positions 21 22 and 23 of the effective virtual address determine the type of shift as f...

Page 77: ...fted left C places Bits shifted past bit position a of register R are copied into bit position 31 of reg ister Ru1 No bits are lost If Cis negative the contents of registers Rand Rul are shifted right...

Page 78: ...specified indexed register determine the direction and amount of the shift If indirect addressing and indexing are called for in the in struction bits 15 31 of the reference address are used to acces...

Page 79: ...peration the floating point result is loaded back into the general register s If the number was originally negative the twols complement of the resu Itant number is loaded into the general register s...

Page 80: ...ruction Condition code settings o 2 3 4 Resu It in R 0 0 Zero 0 Bit 0 of register R is a 1 OBit 0 of register Ris a 0 and bit positions 1 31 of register R contain at least one 1 Sum is correct less th...

Page 81: ...ion an abnormal zero is treated the same as any nonzero operand 3 A positive floating point number is normalized if and only if the fraction is contained in the interval 1 16 F 1 4 A negative floating...

Page 82: ...e hardware and software identi ca I resu Its FR bit 4 of PSWs must be zero 76 Floating Point Arithmetic Instructions F Hexadecimal Value 1111 1111 1111 1111 7F FFFFFF 0000 0000 0000 0000 43 500000 000...

Page 83: ...plies only if FN 0 FZ 0 FZ 1 If the final result of en addition or subtrac tion operation cannot be expressed in normal ized form because of the characteristic being reduced below zero underflow has o...

Page 84: ...c overflow occurs the basic processor always traps to location X 44 with the general registers unchanged and the condition code set to 0110 if the result is positive or to 0101 if the result is negati...

Page 85: ...r R are loaded into a set of internal registers FLOATING SUBTRACT SHORT forms the two1s complement of the effective word and then operates identically to FLOATING ADD SHORT FAS If no floating point ar...

Page 86: ...ndex alignment The effective word divisor and the contents of register R dividend are loaded into a set of internal registers and both numbers are then prenormalized if necessary A normalized 6 digit...

Page 87: ...as a single 16 byte register The entire decimal accumulator is used in every decimal arithmetic instruction DECIMAL INSTRUCTION FORMAT The general format of a decimal instruction is as follows The ind...

Page 88: ...hat contains the most significant byte high order digits of the decimal number and the effective byte address plus L l where L 16 points to the least significant byte low order digit and sign of the d...

Page 89: ...f the sum is equal to or greater than 1031 in which case CCl is reset to 0 CC2 is set to 1 and the instruction aborted with the previous contents of the decimal accumulator CC3 and CC4 unchanged Affec...

Page 90: ...xecution of DECIMAL DIVIDE 1 The divisor must not be zero 2 If the length of the dividend is greater than 15 decimal digits the absolute value of the significant digits to the left of the 15th digit p...

Page 91: ...ight shift Affected DECA CC Trap Decimal arithmetic Condition code settings 2 3 4 Result in DECA o Illegal digit or sign detected instruction aborted o 0 0 Zero o 0 Negative o 0 Positive o 0 Right shi...

Page 92: ...he resulting sign remains unchanged Affected EBltoEBL 2L 2 Trap Decimal arithmetic CC1 CC2 zoned DECA EBL to EBL 2L 2 Condition code settings 2 3 4 Result of UNPK o Illegal digit or sign detected inst...

Page 93: ...true count from 0 to 255 of the number of bytes involved in the operation This field is decremented by 1 as each byte in the destination byte string is processed A ocount means IIno operation ll with...

Page 94: ...trap occurs resulting in a partially executed instruction the Register Altered indi cator wi be set 88 Byte String Instructions MBS MOVE BYTE STRING Immediate Displacement continue after interrupt MO...

Page 95: ...terminates due to inequality the count in register Rul is one greater than the number of bytes remaining to be compared the source ad dress in register R and the destination address in register Rul in...

Page 96: ...ntents of register R 90 Byte String Instructions Contents of register R l The destination byte string begins with the byte location pointed to by the destination address in register R 1 and is C bytes...

Page 97: ...is specified by the Rfield of the instruction word Case III zero R field Rul 1 Contents of register 1 The destination byte string begins with the byte location pointed to by the destination address i...

Page 98: ...racter replaces the byte in the destination byte string 2 The decimal digit is expanded to zoned decimal format and replaces the pattern byte in the destination byte string 3 The pattern byte remains...

Page 99: ...location X 451 as described above d One of the following editing actions is performed Conditions Action Pattern byte SI X 231 Expand digit to zoned format store in pat tern byte location and set CC4...

Page 100: ...ister R register Rul register 1 the destination byte string and the condition code unchanged The R field of the EBS instruction must be an even value excluding 0 for proper operation of the instructio...

Page 101: ...de is 1011 The new contents of register 1 are X xxx01001 1 Example 3 before execution The initial conditions are identical to example 1 except that the contents of the decimal field are 00 54 32 1 Exa...

Page 102: ...decremented by 1 the contents of the stack remain unchanged Bit positions 33 through 47 of the SPD referred to as the space count contain a 15 bit count 0 to 32 767 of the number of word locations cur...

Page 103: ...instruction is successfully executed CCl and CC3 are reset to 0 at the completion of the instruction Also CC2 and CC4 are independently set to indi cate the current status of the space count and the...

Page 104: ...s a 20 bit field 12 31 for real and virtual addressing modes it is a 17 bit field 15 31 98 Push Down Instructions Non Privileged 3 The space count SPD33 47 is incremented by 1 and the word count SPD49...

Page 105: ...ress is in the range 0 through 15 then the registers indi cated by the Rfield of the PSM in struction are stored in the general registers rather than in main memory In this case the results wi II be u...

Page 106: ...halfword The modifier is alge braica Ily added to the top of stack address subtracted from the space count and added to the word count in the stack pointer doubleword If as a resu It of MSP either th...

Page 107: ...s selected by the hardware wi II contain the basic processor environment Eight locations whose contents are designated as indeterminate in Figure 12 are reserved and must not be used For each PLS inst...

Page 108: ...8 10 19 9 20 8 21 7 22 6 23 5 24 4 25 PSWl 3 26 PSW2 2 27 PSW3 t 1 initial TSA 28 PSW4 initial TSA tAs a function of the hardware the contents of these 8 locations are in determinate after a PSS instr...

Page 109: ...stead the BP traps to location X 4D instruction exception trap and TCC2 is set PSS PUSH STATUS Doubleword index alignment privi leged xl aD PUSH STATUS loads new Program Status Words from an ef fectiv...

Page 110: ...represents inclusive OR ED56 59 RP on Iy if I8 1 ED60 RA ED61 MA 104 Push Down Instructions Privileged Memory Stack General Register n initial TSA n l where n has ascending values from 0 through 15 PS...

Page 111: ...Ws are ORed II with the contents of bit positions 37 38r and 39 of the default PSWs to generate the CI II and EI bits of the new PSWs Depending upon the coding of the CL and AD flags bit positions 10...

Page 112: ...rap un less the instruction that is actually to follow the branch instruc tion is in a protected or nonexistent memory region Traps do not occur because of any anticipation on the part of the hardware...

Page 113: ...instruction is the same as the normal interruptibility for that instruction If a trap condition occurs between the beginning of an EXU instruction or chain of EXU instructions and the comple tion of t...

Page 114: ...R is unavailable to the program slave or master protected mode for instruction access and the branch condition is satisfied or if the effective address of BDR is nonexistent the basi c processor abort...

Page 115: ...and there fore cannot cause a trap CALI CALL 1 Word index alignment CALL 1 causes the basi c processor to trap to location X 48 CAL2 CALL 2 Word index alignment CAL4 CALL 4 Word index al ignment CALL...

Page 116: ...nterrupt level currently in the active state is cleared i e reset to either the armed state or the dis armed state the interrupt level is armed if bit 11 AD 110 Control Instructions of lPSD is a 1 or...

Page 117: ...of a trap entry operation is called a trap instruction Ad dressing is the same as for the interrupt XPSD see above The fol lowing additional operations are performed on the new program status words i...

Page 118: ...as iI hjs ra ed above arE replaced by new program status words as described below 1 The effective address of XPSD is incremented by 2 so that it points to the next doubleword location The contents of...

Page 119: ...sor traps to location X 4D Affected RP Trap Instruction exception EW 24 _ 27 RP MOVE TO MEMORY CONTROL INSTRUCTIONS The following instructions may be used to sel ectively move a string of control word...

Page 120: ...map image either a bit or 11 bit for mat contents of register Ru 1 are For loading 4 bit write lock images contents of register Ru1 are For loading access protection or 2 bit write lock images content...

Page 121: ...on codes for 16 consecu tive pages of virtual memory Thus the access protection control image for 128K word 256 page virtual memory is contained within 16 contiguous memory locations desig nated as th...

Page 122: ...n equivalent num ber of write lock registers the lock image address is incre mented by one Thus successive image words are accessed in an ascending sequence Depending upon the instruction format the h...

Page 123: ...of the LRA instruction and loads that real address and status information as listed below into register R Upon comple tion of the LRA instruction additional information pertain ing to the LRA instruct...

Page 124: ...0 Read and inhibit parity loads the effective word into R If a memory parity error is de tected the memory does not take a snapshot 11 or generate a Memory Fau It Interrupt MFI 118 Control Instruction...

Page 125: ...arting address bit 15 11 Starting address bit 16 12 Starting_ address bit 17 13 Starting address bit 18 14 Reserved 15 31 Address received bits 15 31 WAIT WAIT Word index al ignment privileged WAIT ca...

Page 126: ...If the R field of RD is nonzero up to 32 bits of the returned data are loaded into general regis ter R however if the R field of RD is 0 the returned data is ignored and general register ais not chang...

Page 127: ...y be used Q Address Contents X lD X lP Bits 0 13 Reserved Bits 14 31 Branch from Program Counter Bits 0 7 Reserved Bits 8 31 Load Device Address All other Q addresses from X OO X lF are reserved Affec...

Page 128: ...ce 122 Control Instructions WRITE DIRECT INTERNAL BASIC PROCESSOR CONTROL MODE 0 LOAD SENSE SWITCHES The fol lowing configuration of WD can be used to load the sense switches in the System Control Pro...

Page 129: ...able 14 Real Time Clock 1 S 1 Starting Address S12 15 Real Time Clock 2 S0 Starting Address S13 16 Real Time Clock 2 S 1 Starting Address S14 17 Real Time Clock 3 S0 Starting Address S15 18 Real Time...

Page 130: ...served 1 0 0 0 1 Reserved 1 0 0 1 0 Reserved 1 0 0 1 1 Reserved 1 0 1 0 0 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 Reserved 1 0 1 1 1 Reserved Memory Un its 0 1 0 0 0 Memory UnitType 1 0 1 0 0 1 Reserved...

Page 131: ...WD instruction resets it A program can thus generate a desired frequency by setting and resetting the PCF flip flop at the appropriate rate Execution of the above configuration of WD also re sets the...

Page 132: ...nterrupt groups bit 16 of register R contains the selection bit for the highest priority lowest numbered interrupt level within the group and bit 31 of register R contains the selection bit for the lo...

Page 133: ...ved Further detai Is of I o instructions are illustrated in Figure 13 and de scribed in Table 13 I O STATUS INFORMATION SIO TIO TDY AND HIO INSTRUCTIONS If the R field is coded with a 0 no status info...

Page 134: ...Instructions Bit Applicable Instructions Position Mnemonics Function and or Description 0 A I O instructions If this bit is a 1 bits 15 31 of the initla Vo instruction are modified by in direct addre...

Page 135: ...struction the required I o address may be comprised of 1 a cluster address 2 a cluster address and a unit addressi 3 a cluster address a uni t address and a device controll er addressi or 4 a cluster...

Page 136: ...Status Information Register R Table 14 I o Status Information Register R cont Bit Position Significance Position Significance o Reserved t Bus Check Fault BCF This bit is set to 1 if a discrepancy exi...

Page 137: ...ped some condi tion that wi II not allow it to proceed in either case operator intervention is usually required If bits 1 and 2 are 10 device un avai lable the device has more than one channel of comm...

Page 138: ...gth condition occurred within the responding subchannel An incorrect length condition is caused by a IIchannel end or end of record condition occurring before the device controller has a count done si...

Page 139: ...erminate immediately as an II unusuaI endll 15 This bit is set to a 1 if a Write Lock Violation WLV occurs Table 17 Status Response Bits for I O Instructions Position and State in Register Ru 1 Device...

Page 140: ...ion occurring before the device controller has a count done signal from the lOP indicating that 134 Input Output Instructions Table 18 lOP Status Byte cont Bit Position Significance 8 the byte count h...

Page 141: ...T OUTPUT performs the following 1 Attempts to initiate an input or output operation whether an I O operation is started or not is dependent upon conditions within the addressed I o subsystem see meani...

Page 142: ...information in general registers may be incorrect For MIOP not possible o Processor Interface detected parity error on returned status and or condition code The result of the SIO is indeterminate 136...

Page 143: ...peration BCF detected while unit performing a Data In operation TDV TEST DEVICE Word index alignment privileged TEST DEVICE is used to provide information about a device other than that obtainable by...

Page 144: ...indirect address location bits 15 16 and 17 must specify the desired operation code extension 138 Input Output Instructions If the R field of the HIO instruction is 0 the condition code is set but no...

Page 145: ...ng processors i e BP MIOP and or RMP In a monoprocessor system cluster address XIO I is assi gned to the c luster containing the basic processor BP Cluster address X I is assigned only to the cluster...

Page 146: ...ore flags are coded to ClJuse lJn nterrupt for two or more conditions an interrupt is requested whenever any of the IIflaggedll conditions is detected For some conditions transmission errors incorrect...

Page 147: ...rror on returned status and or condition code The result of the Ala is indeterminate o 0 Processor interface detected o 0 0 Unusual condition interrupt recognized and reset Status information in gener...

Page 148: ...troller Depending upon the number and type of I o devices to be connected one or 142 Input Output Operations more of the following types of device controllers may be connected to an MIOP 1 Single unit...

Page 149: ...IST Each I O operation performed by an lOP must be defined by a command list The characteristics and requirements of a command list are as follows 1 It is normally created by a BP executed program pri...

Page 150: ...ational 10CD all parameters except the I o order are updated and the device controller device con tinue to operate as if the I o operation were defined by a single 10CD i e the data chain operation is...

Page 151: ...peration 1 Memory Address Error MAE 2 lOP Control Error IOPCE 3 Control Check Error CCF 4 lOP Memory Error IOPME 5 Bus Check Fault BCF whi Ie fetching an 10CD 6 Memory interface Error MIE whi Ie fetch...

Page 152: ...y a memory unit When the lOP receives a WLV signal the WLV bit within the status information register is set to 1 and remains set until a new I o operation is initiated within this I O sub channel by...

Page 153: ...been pu nched The command address register within the I o subchannel is incremented by two by the chain modifier signal and the next consecutive lOCO within the command list is skipped over not fetch...

Page 154: ...peration An HIO may leave the device in an unpredictable state an RIO resets all controllers and devices on the addressed lOP As a result of accepting an SIO instruction a command ad dress register wi...

Page 155: ...e ignored Other Control orders e g Rewind for a magnetic tape unit are listed and described in applic able Xerox peripheral equipment reference manuals Depending upon the control function performed ce...

Page 156: ...information Instead the lOP generates and loads zeros XIOOI into the data buffers of the appropriate I O subchannel and increments the memory byte address and decrements the byte count by one for 150...

Page 157: ...mmand is entered from the System Con trol Console SCC The progress of an I O operation including the termination may be ascertained by evaluating the status information returned for I O instructions a...

Page 158: ...mote consoles share the same data paths Both consoles receive the some output either one of the consoles is selected for input by the ALTSEL switch on the Configuration Control Panel The communication...

Page 159: ...the system provides an odvisory message following the com mand echo indicating the probable source of error A typi cal example of the display format is II RSY EVENT A1 1I indicating that a reset comm...

Page 160: ...ed by indicators on the System Control Panel The SET SENSE SWITCHES command is always operative The sense switches may also be set by executing a WRITE DIRECT instruction see Chapter 3 The sense switc...

Page 161: ...the function described below 1 The system control processor bus interface is initialized 2 The processor memory bus and processor bus interfaces are initialized 3 The system memory units are initiali...

Page 162: ...e commands If the character is not in the allowed commond set it is echoed followed by a question mark II N and no action results Valid commands are echoed the requested operation is then performed an...

Page 163: ...ation or Q register for each R command executed Actual contents of the memory or Q register location ref erenced by the shift instruction are not altered P Mode I INCREMENT REFERENCED ADDRESS AND DISP...

Page 164: ...intout in the format II CE DDDDDDDD CC The II CEil field contains two hexadecimal digits that represent a cluster and an element address respectively The 8 digit D field displays the contents of the r...

Page 165: ...issued The contents of the currently selected Single Clock Status Register are displayed The clock step counter is incremented by the number of clock steps specified by this command The MULTIPLE CLOCK...

Page 166: ...n is entered The P Mode Repeat Mode may be reset by a CLEAR P MODE REPEAT MODE ZCMM3 a CLEAR MM FEATURES ZCMMO or a SUPER RESET ZCMN t4 command 160 Control Commands The P Mode repeat feature is partic...

Page 167: ...Inhibit Mode is normally set to inhibit print out during execution of SCC functions which do not require a display The Display Inhibit Mode may be cleared by a CLEAR DISPLAY INHIBIT MODE ZCMMA a CLEAR...

Page 168: ...inated whenever the system clock frequency is above or below the normal value usually as a result of maintenance and or diagnostic activities see SET LOW CLOCK MARGINS and SET HIGH CLOCK MARGINS comma...

Page 169: ...this switch is in the SCC position the alternate and remote consoles may be connected in parallel with the System Control Console and may perform the same control func tions as the local control devic...

Page 170: ...Length SIL flag is set to 1 so that an incorrect length in dication will not cause a Transmission Error Halt After the SIO instruction has been executed the basic processor executes a no instruction...

Page 171: ...t is a 0 the basic processor will automatically retry the instruction which caused the trap to location X 4C if this bit is a 1 the basic processor is inhibited from retrying the instruction which cau...

Page 172: ...y cycles 2 1 Selects comparisons only during memory write cycle 0 Selects all memory cycle comparisons 3 1 Selects page comparisons 0 Selects word comparisons 4 1 System turns on audible alarm for 220...

Page 173: ...ic assocIated with each row of switches and indicators is located within each pro cessor cluster or memory unit itself Above each row is a marker strip that identifies the function of each switch The...

Page 174: ...ast significant bit designates the back panel location in the halves of the cabinet POWER POWER SYSTEM CLOCK NNORM ON SEL SEL Figure 16 Chassis Physical Configuration PROCESSOR I ADDRESS BP MIOP DIO E...

Page 175: ...ers Note The 5 bit chassis location number and not the processor address is used in addressing the configuration switches for a given unit by the RD instruction directed to the Con figuration Control...

Page 176: ...he unit reset signal When in down position power to unit is off Determines to which central shared resources the reset signal is connected Selects which clock the memory shall use up position selects...

Page 177: ...e sizes that are powers of two they can all be different they must however be assigned in order of decreasing size in the address continuum For instance three memory units can be used in this manner M...

Page 178: ......

Page 179: ...ommand Three types of code are shown 1 the 8 bit Xerox Standard Computer Code i e the Extended Binary Coded Decimal Interchange Code EBCDIC 2 the 7 bit American National Standard Code for Information...

Page 180: ...in the 63 and 89 character EBCDIC sets but not in either of the ANSCIl based sets However Xerox software translates the characters into ANSCII characters as follows EBCDIC l I ANSCII 6 0 7 12 7 14 Th...

Page 181: ...d or new line 16 22 SYN 11 9 6 1 6 sync 17 23 ETB 11 9 7 1 7 end of transmission block 18 24 CAN 11 9 8 1 8 cancel 19 25 EM 11 9 8 1 1 9 end of medium lA 26 SUB 11 9 8 2 1 10 substitute Replaces chara...

Page 182: ...2 9 right parenthesis 5E 94 11 8 6 3 11 semicolon SF 95 or 11 8 7 7 14 tilde or logical not 60 96 11 2 13 minus dash hyphen 61 97 0 1 2 15 slash 62 98 11 0 9 2 62 through 69 will not be assigned 63 99...

Page 183: ...12 11 9 7 2 9A 154 12 11 8 2 9A through Al are unassigned 9B 155 12 11 8 3 9C 156 12 11 8 4 9D 157 12 11 8 5 9E 158 12 11 8 6 9F 159 12 11 8 7 AO 160 11 0 8 1 A1 11 1 11 0 1 A2 162 s 11 0 2 7 3 A3 163...

Page 184: ...through DF will not be assigned DB 219 12 11 9 8 3 DC 220 12 11 9 8 4 DD 221 12 11 9 8 5 DE 222 12 11 9 8 6 DF 223 12 11 9 8 7 EO 224 0 8 2 EO El are unassigned El 225 11 0 9 1 E2 226 S 0 2 5 3 E3 227...

Page 185: ...1A 1B D OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C E OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E MULTIPLICATION TABLE 1 2 3 4 5 6 7 8 9 A B C D E F 2...

Page 186: ...40625 x 10 8 0 23283 06436 53869 62891 x 10 9 0 14551 91522 83668 51807 x 10 10 0 90949 47017 72928 23792 x 10 12 0 56843 41886 08080 14870 x 10 13 0 35527 13678 80050 09294 x 10 14 0 22204 46049 250...

Page 187: ...4 000 81920 600000 6 291 456 15000 86 016 700 000 7340032 Example Convert 0 89510 to its hexadecimal equivalent 16000 90 112 800 000 8388 608 0 895 17000 94208 900000 9437 184 18000 98304 AOO 000 10 4...

Page 188: ...0614 0615 0616 0617 0618 0619 0620 0621 0622 0623 270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 06...

Page 189: ...1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 14...

Page 190: ...2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 21...

Page 191: ...2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 B80 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 29...

Page 192: ...686 3687 3688 3689 3690 3691 3692 3693 3694 3695 E70 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 E80 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 372...

Page 193: ...0 5E 000000 3671875000 9E 000000 6171875000 DE 000000 8671875000 IF 000000 1210937500 5F 000000 3710937500 9F 000000 6210937500 DF 000000 8710937500 20 000000 1 2500 00000 60 000000 37500 00000 AO 00...

Page 194: ...00 00045 77636 00 5E 00 00 0014343261 00 9E 00 00 00241 08886 00 DE 0000 00338 74511 00 IF 00 00 00047 30224 00 5F 00 00 00144 95849 00 9F 00 00 0024261474 00 DF 0000 00340 27099 00 20 00 00 00048 828...

Page 195: ...00 00000 56028 0000 9E 00 00000 94175 00 00 DE 00 00001 32322 0000 IF 00 00000 18477 0000 5F 00 00000 56624 00009F 00 00000 94771 00 00 DF 00 00001 32918 000020 CO cccce 9073 1 nn Lr r wwAO w VVVUU 95...

Page 196: ...E 00000 00218 00 00 00 9E 00000 00367 00 00 00 DE 00000 00516 000000 IF 00000 00072 0000005F 00000 00221 000000 9F 00000 00370 00 00 00 DF 00000 0051 9 00000020 00000 00074 I 0000 00 60 00000 00223 00...

Page 197: ...854 715 202 003 717 422 485 351 562 5 140 737 488 355 328 47 0 000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25 281 474 976 710656 48 0 000 000 000 000 003 552 713 678 800 500 929 355 6...

Page 198: ...ess field bit position 31 is automatically 192 Appendix B Term EDL cont EDO EH Meaning forced to O Hence odd numbered word address referring to middle of doubleword designates same doubIeword as even...

Page 199: ...ap Reference address contents of bit posi tions 15 31 of instruction word a 17 bit field capable of directly addressing any Term Ref Add cont RP Ru1 SA SBS SE SPD TCC TS TSA TW Meaning general registe...

Page 200: ...struction word In instruction word if X 0 no indexing is performed 194 Appendix B Term X cont Xln l Meaning if X f 0 indexing is performed after indirect addressing if indirect addressing is called fo...

Page 201: ...rved Error MIE typet 8 24 Processor interface ControIMemory Reserved Reserved Control Memory Reserved sequence check Fault CMF Fault CMF fault address bit 0 address bit 0 9 25 Extended arithmetic CMF...

Page 202: ...s snapshot 22 Reserved 23 Memory unit parity error 24 Storage module selection error 25 Address In parity error 26 Data In parity error 27 Write lock memory storage parity error 28 Port seIection erro...

Page 203: ...L PUBLICATION NO 9030 76A JANUARY 1974 Page 9 should be replaced with the page attached to this revision sheet Page 10 is a backup page with no change The revision bar in the margin of the page indica...

Page 204: ...vered DWell o Well Organized o Clear Illustrated o Reference o Maintaining 0 Operating What is your overall rating of this publication What is your occupation o Very Good 0 Fair o Very Poor o Good o P...

Page 205: ...s Fold BUSINESS REPLY MAIL No postage stamp necessary if mailed in the United States Postage will be paid by Xerox Corporation 701 South Aviation Boulevard EI Segundo California 90245 vU lfJlt First C...

Page 206: ...701 South Aviation Boulevard EI Segundo California 90245 213679 4511 XEROX XEROX is a trademark of XEROX CORPORATION...

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