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SMSC USB2250/50i/51/51i

DATASHEET

Revision 1.1 (05-29-08) 

Datasheet

PRODUCT FEATURES

USB2250/50i/51/51i 

Ultra Fast USB 2.0 Multi-Slot 
Flash Media Controller

General Description

The SMSC USB2250/50i/51/51i is a USB 2.0 compliant, high
speed Mass Storage Class Peripheral Controller intended for
reading and writing to 

more than

 

24

 

popular flash media

formats from the

 

CompactFlash

®

 (CF), SmartMedia

TM

 (SM),

 

xD

Picture Card

TM

 (xD)

1

, Memory Stick

TM

 (MS), Secure Digital

(SD), and MultiMediaCard

TM

 (MMC) families. 

The SMSC USB2250/50i/51/51i is a fully integrated, single
chip solution capable of ultra high performance operation.
Average sustained transfer rates exceeding 35MB/s are
possible if the media and host can support those rates. 

General Features

„

128-pin VTQFP (14x14mm) 

lead-free RoHS compliant 

package

„

Targeted for applications in which single or "combo" media 

sockets are used

„

Supports multiple simultaneous card insertions

„

Flexible assignment of number of LUNs and how card types 

are associated with the LUNs

„

Hardware-controlled data flow architecture for all self-

mapped media

„

Pipelined hardware support for access to non-self-

mapped media

„

Product name with “i” denotes the version that supports 

the industrial temperature range of -40ºC to 85ºC

Hardware Features

„

Single Chip Flash Media Controller with non-multiplexed 

interface for independent card sockets 

„

Flash Media Specification Revision Compliance

Compact Flash Specification 4.1

CF UDMA Modes 0-4

CF PIO Modes 0-6

Memory Stick Specification 1.43

Memory Stick Pro Format Specification 1.02

Memory Stick Pro-HG Duo Format Specification 1.01

Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro

xD Picture Card 1.2

Smart Media Specification 1.3

Secure Digital 2.0

HS-SD, HC-SD, TransFlash™ and reduced form factor 
media 

MultiMediaCard Specification 4.2

1/4/8 bit MMC

„

SDIO and MMC Streaming Mode support

„

Extended configuration options

xD player mode operation 

Socket switch polarities, etc.

„

Media Activity LED

„

GPIO configuration and polarity

Up to 11 GPIOs (based on configuration) for special 
function use: LED indicators, button inputs, power 
control to memory devices, etc. The number of actual 
GPIO’s depends on the implementation configuration 
used.

Four GPIO’s with up to 200 mA drive

An additional 16 GPIO’s if CF is not used

„

On Board 24MHz Crystal Driver Circuit

„

Optional external 24MHz clock input

„

4 Independent Internal Card Power FET

200mA each

"Fold-back" short circuit current protected

„

8051 8-bit microprocessor

60MHz - single cycle execution

64KB ROM; 14KB RAM

„

Internal Regulator for 1.8V core operation

„

Optimized pinout improves signal routing, easing 

implementation and allowing for improved signal integrity

OEM Selectable

 Features

„

VID/PID/Language ID

„

28-character Manufacturer ID and Product string

„

12-hex digit (max) Serial Number string

„

Customizable Vendor specific data 

by optional use of 

external serial EEPROM

„

Bus- or Self-powered selection

„

LED blink interval or duration

„

Internal power FET configuration

Software Features

„

Optimized for low latency interrupt handling

„

Reduced memory footprint

„

Device Firmware Upgrade (DFU) support of external 

EEPROM or External Flash

Assembly line support

End user field upgrade support

DFU Package consists of driver, firmware, sample DFU 
application and source code, DFU driver API

„

Optional custom firmware with external ROM (up to 128k)

„

Please see the USB2250/50i/51/51i

 

Software Release 

Notes for additional Software Features.

Applications

„

Flash Media Card Reader/Writer

„

Printers

„

Desktop and Mobile PCs

„

Consumer A/V

„

Media Players/Viewers

„

Vista ReadyBoost

TM

1.) xD Picture Card not applicable to USB2251.

Summary of Contents for USB2250

Page 1: ...Digital 2 0 HS SD HC SD TransFlash and reduced form factor media MultiMediaCard Specification 4 2 1 4 8 bit MMC SDIO and MMC Streaming Mode support Extended configuration options xD player mode operation Socket switch polarities etc Media Activity LED GPIO configuration and polarity Up to 11 GPIOs based on configuration for special function use LED indicators button inputs power control to memory ...

Page 2: ...d authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval of an Officer of SMSC and further testing and or modification will be fully at the risk of the customer Copies of this document or other SMSC literature as well as the Terms of Sa...

Page 3: ...tion 10 Chapter 5 Pin Descriptions 11 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions 11 5 2 Buffer Type Descriptions 20 Chapter 6 Pin Reset State Table 21 6 1 128 Pin Reset States 22 Chapter 7 DC Parameters 28 7 1 Maximum Guaranteed Ratings 28 7 2 Recommended Operating Conditions 29 7 3 DC Electrical Characteristics 30 7 4 Capacitance 32 Chapter 8 AC Specifications 33 8 1 Oscillator Clock 3...

Page 4: ... Figure 4 1 USB2250 50i 51 51i 128 Pin VTQFP Diagram 10 Figure 6 1 Pin Reset States 21 Figure 6 2 Legend for Pin Reset States Table 21 Figure 6 3 USB2250 50i 51 51i Pin Reset States 22 Figure 7 1 Supply Rise Time Model 29 Figure 8 1 Typical Crystal Circuit 33 Figure 8 2 Formula to Find Value of C1 and C2 33 Figure 9 1 USB2250 50i 51 51i 128 Pin VTQFP 14x14x1 0mm Body 2 0mm Pitch 34 ...

Page 5: ...vision 1 1 05 29 08 DATASHEET List of Tables Table 0 1 USB2250 50i 51 51iComparison of Features 2 Table 3 1 USB2250 50i 51 51i 128 Pin VTQFP Package 8 Table 5 2 USB2250 50i 51 51i Buffer Type Descriptions 20 Table 7 1 Pin Capacitance 32 Table 10 1 USB2250 50i 51 51i GPIO Usage ROM Rev 0x00 35 ...

Page 6: ... other agreement with any customer or otherwise with respect to infringement including without limitation any obligations to defend or settle claims to reimburse for costs or to pay damages shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices or to any combinations involving any of them with respect to infringement or claim...

Page 7: ...SSOR SFR RAM CF GPIO 16 MS SM RAM USB Host AUTO_ CBW PROC PHY FMI XDATA BRIDGE BUS ARBITER BUS INTFC BUS INTFC BUS INTFC EP0 TX EP0 RX EP2 TX EP2 RX EP1 RX EP1 TX ROM 64KB RAM 10KB ADDR MAP GPIOs Program Memory I O Bus PWR_FET0 PWR_FET1 PWR_FET3 PWR_FET2 11 pins GPIO8 CARD_PWR0 GPIO9 CARD_PWR1 GPIO11 CARD_PWR3 1 8V Reg Clock Generation and Control PLL GPIO10 CARD_PWR2 SD MMC 4K total ROM is not av...

Page 8: ...CF_D13 GPIO29 CF_D14 GPIO30 CF_D15 GPIO31 CF_nIOR CF_nIOW CF_IRQ CF_nRESET CF_IORDY CF_nCS0 CF_DMACK TXD GPIO7 CF_SA0 CF_SA1 CF_SA2 GPIO13 CF_nCD CF_DMARQ RXD GPIO2 SMARTMEDIA INTERFACE 17 PINS SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_ALE SM_CLE SM_nRE SM_nWE SM_nWP SM_nB R SM_nCE GPIO14 SM_nCD SM_nWPS MEMORY STICK INTERFACE 11 PINS MS_BS MS_D0 MS_SDIO MS_SCLK GPIO12 MS_INS MS_D1 MS_D2 M...

Page 9: ...L1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 nMRD nMWR nMCE MISC 10 PINS nRESET GPIO3 VBUS_DET GPIO4 SCL xD_ID GPIO5 SDA LED1 GPIO1 GPIO8 CARD_PWR0 GPIO9 CARD_PWR1 GPIO10 CARD_PWR2 GPIO11 CARD_PWR3 TEST DIGITAL POWER 14 PINS 5 VDD33 1 VDD18 8 VSS TOTAL 128 Table 3 1 USB2250 50i 51 51i 128 Pin VTQFP Package continued ...

Page 10: ...3 SM_CLE 52 SM_ALE 51 VSS 50 VDD33 49 VDD18 48 SM_nWE 47 SM_nWP 46 SM_D0 45 SM_D1 44 SM_D2 43 SM_D3 42 SM_D4 41 SM_D5 40 SM_D6 39 SM_D7 38 SM_nWPS 37 MD0 36 MD1 35 MD2 34 MD3 33 MD7 96 MS_D2 95 MS_D4 94 MS_D0 MS_SDIO 93 MS_D5 92 MS_D1 91 MS_BS 90 CF_D10 GPIO26 89 CF_D9 GPIO25 88 CF_D2 GPIO18 87 CF_D8 GPIO24 86 CF_D1 GPIO17 85 CF_D0 GPIO16 84 CF_SA0 83 CF_SA1 82 CF_SA2 81 VSS 80 CF_IORDY 79 CF_nRES...

Page 11: ...Descriptions Table 5 1 USB2250 50i 51 51i 128 Pin VTQFP Pin Descriptions NAME SYMBOL 128 PIN VTQFP BUFFER TYPE DESCRIPTION COMPACT FLASH INTERFACE CF Chip Select 0 CF_nCS0 71 O12 This pin is the active low chip select 0 signal for the task file registers of the CF ATA device in True IDE mode CF Register Address CF_SA 2 0 82 83 84 I O12 These pins are the register select address bits for the CF ATA...

Page 12: ...t signal to the CF device CF IO Read CF_nIOR 72 O12 This pin is an active low read strobe signal for the CF device CF IO Write Strobe CF_nIOW 73 O12 This pin is an active low write strobe signal for the CF device CF DMA request CF_DMARQ RXD GPIO2 117 I CF_DMARQ This pin is the DMA request from the device to the CF controller RXD The signal can be used as input to the RXD of UART in the device when...

Page 13: ...al weak pull up resistor that is tied to the output of the internal Power FET and is controlled by the SM_PU bit of the SMC_CTL register If an external FET is used Internal FET is disabled then the internal pull up is not available external pull ups must be used SM Write Enable SM_nWE 48 O12PU This pin is an active low write strobe signal for SM device When using the internal FET this pin has an i...

Page 14: ...rnal pull ups must be used SM Card Detection GPIO GPIO14 SM_nCD 57 I O12 This is a GPIO designated as the Smart Media card detection pin MEMORY STICK INTERFACE MS Bus State MS_BS 91 O12 This pin is connected to the BS pin of the MS device It is used to control the Bus States 0 1 2 and 3 BS0 BS1 BS2 and BS3 of the MS device MS Card Insertion GPIO GPIO12 MS_INS 98 IPU This is a GPIO designated as th...

Page 15: ... directional signals should have weak pull up resistors The register can be controlled by the SD_MMC_INTF_EN bit of SDC_MODE_CTL SD Clock SD_CLK 18 O12 This is an output clock signal to the SD MMC device The clock frequency is software configurable SD Command SD_CMD 20 I O12PU This is a bi directional signal that connects to the CMD signal of the SD MMC device The bi directional signal should have...

Page 16: ...an the crystal circuit 1 8V PLL Power VDD18PLL 125 This pin is the 1 8V Power for the PLL If the internal regulator is enabled then this pin must have a 1 0μF or greater 20 ESR 0 1Ω capacitor to VSS 3 3V Analog Power VDDA33 128 3 3V Analog Power MEMORY IO INTERFACE Memory Data Bus MD 7 0 33 29 30 31 34 35 36 37 I O12 These signals are used to transfer data between the internal CPU and the external...

Page 17: ... the corresponding MA pin will function identically to the MA 15 3 pins at all times other than during nRESET assertion Memory Write Strobe nMWR 3 O12 Program Memory Write active low Memory Read Strobe nMRD 115 O12 Program Memory Read active low Memory Chip Enable nMCE 26 O12 Program Memory Chip Enable active low This signal is asserted when any external access is being done by the processor This ...

Page 18: ... or output I O200 CRD_PWR Card Power drive of 3 3V either 100mA or 200mA General Purpose I O GPIO10 CRD_PWR2 76 I O12 GPIO These pins may be used either as input edge sensitive interrupt input or output It is a requirement that this is the only FET used to power SM devices Failure to do this will violate SM voltage specification on SM device pins I O200 CRD_PWR Card Power drive of 3 3V either 100m...

Page 19: ...controlling pull up down resistors associated with the pins as well as the individual card control registers DIGITAL POWER and GROUND 1 8V Digital Core Power VDD18 49 All VDD18 pins must be connected together on the circuit board 1 8V Core power If the internal regulator is enabled then this pin must have a 1 0μF or greater 20 ESR 0 1Ω capacitor to VSS 3 3V Power Voltage Regulator Input VDD33 15 5...

Page 20: ... and 12mA source I O200 Input Output buffer 12mA with FET disabled 100 200mA source only when the FET is enabled I O12PD Input Output buffer with 12mA sink and 12mA source with an internal weak pull down resistor I O12PU Input Output buffer with 12mA sink and 12mA source with a pull up resistor O12 Output buffer with 12mA source O12PU Output buffer with 12mA sink and 12mA source with a pull up res...

Page 21: ...l v Time t RESET RESET Hardware Initialization Firmware Operational VDD33 VSS LEGEND yes hardware enables function hardware disables function z hardware disables output driver pu hardware enables pullup pd hardware enables pulldown hw hardware controls function but state is protocol dependent fw firmware controls function through registers VDD hardware supplies power through pin applicable only to...

Page 22: ...88 CF_D2 GPIO18 GPIO z CF hw pd hw GPIO fw fw fw 59 CF_D3 GPIO19 GPIO z CF hw pd hw GPIO fw fw fw 61 CF_D4 GPIO20 GPIO z CF hw pd hw GPIO fw fw fw 63 CF_D5 GPIO21 GPIO z CF hw pd hw GPIO fw fw fw 67 CF_D6 GPIO22 GPIO z CF hw pd hw GPIO fw fw fw 69 CF_D7 GPIO23 GPIO z CF hw pd hw GPIO fw fw fw 87 CF_D8 GPIO24 GPIO z CF hw pd hw GPIO fw fw fw 89 CF_D9 GPIO25 GPIO z CF hw pd hw GPIO fw fw fw 90 CF_D1...

Page 23: ...17 CF_DMARQ RXD GPIO2 GPIO 0 CF z pd yes GPIO fw fw fw RXD z fw yes 58 GPIO13 CF_nCD GPIO z pu yes GPIO fw fw fw 46 SM_D0 SM z pd SM hw pd yes 45 SM_D1 SM z pd SM hw pd yes 44 SM_D2 SM z pd SM hw pd yes 43 SM_D3 SM z pd SM hw pd yes 42 SM_D4 SM z pd SM hw pd yes 41 SM_D5 SM z pd SM hw pd yes 40 SM_D6 SM z pd SM hw pd yes 39 SM_D7 SM z pd SM hw pd yes RESET STATE Post Reset State xD Mode Post Reset...

Page 24: ... pd yes 92 MS_D1 MS z pd MS hw hw yes 96 MS_D2 MS z pd MS hw pd yes 99 MS_D3 MS z pd MS hw pd yes 95 MS_D4 MS z pd MS hw pd yes 93 MS_D5 MS z pd MS hw hw yes 97 MS_D6 MS z pd MS hw pd yes 100 MS_D7 MS z pd MS hw pd yes 98 GPIO12 MS_INS GPIO z pu yes GPIO fw fw fw 20 SD_CMD SD z SD hw pu yes 18 SD_CLK SD z SD hw yes 12 SD_D0 SD z SD hw pu yes RESET STATE Post Reset State xD Mode Post Reset State SD...

Page 25: ...D_WP GPIO 0 GPIO fw fw fw 32 GPIO15 SD_nCD GPIO z pu yes GPIO fw fw fw 27 MA0 CLK_SEL0 MA z pd yes MA hw 25 MA1 CLK_SEL1 MA z pd yes MA hw 116 MA2 MA z pd yes MA hw 114 MA3 MA z pd yes MA hw 112 MA4 MA 0 MA hw 110 MA5 MA 0 MA hw 108 MA6 MA 0 MA hw 106 MA7 MA 0 MA hw 109 MA8 MA 0 MA hw 111 MA9 MA 0 MA hw RESET STATE Post Reset State xD Mode Post Reset State SD Mode Post Reset State MS Mode PIN PIN ...

Page 26: ...pu MA hw hw hw 29 MD6 MA z pu MA hw hw hw 33 MD7 MA z pu MA hw hw hw 115 nMRD MA 1 MA hw 26 nMCE MA 1 MA 0 120 LED1 GPIO1 GPIO 0 GPIO fw fw fw 118 GPIO4 SCL xD_ID GPIO 0 GPIO fw fw fw 14 GPIO8 CARD_PWR0 GPIO z GPIO fw fw fw PWR VDD 78 GPIO9 CARD_PWR1 GPIO z GPIO fw fw fw PWR VDD 76 GPIO10 CARD_PWR2 GPIO z GPIO fw fw fw PWR VDD RESET STATE Post Reset State xD Mode Post Reset State SD Mode Post Rese...

Page 27: ...A 1 MA hw 121 GPIO3 VBUS_DET GPIO z yes GPIO fw fw fw 5 GPIO5 SDA GPIO 0 pu GPIO fw fw fw 55 SM_nRE SM z SM hw fw 48 SM_nWE SM z SM hw fw 56 SM_nB R SM z SM z fw yes 54 SM_nCE SM z SM hw fw 7 USB USB z USB z hw hw 8 USB USB z USB z hw hw 127 RBIAS 124 XTAL1 CLKIN 123 XTAL2 6 REG_EN RESET STATE Post Reset State xD Mode Post Reset State SD Mode Post Reset State MS Mode PIN PIN NAME FUNCTION OUT PUT ...

Page 28: ...oltage spikes on their outputs when the AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output When this possibility exists it is suggested that a clamp circuit be used PARAMETER SYMBOL MIN MAX UNITS COMMENTS Storage Temperature TA 55 150 C Lead Temperature 325 C Soldering 10 seconds 3 3V supply voltage VDD33 VDDA33 0 5 4 0 V Voltage on USB a...

Page 29: ...ator with an output tolerance of 1 must be used if the output of the internal power FET s must support a 5 tolerance PARAMETER SYMBOL MIN MAX UNITS COMMENTS Operating Temperature Commercial Part Industrial Part TA TA 0 40 70 85 C C 3 3V supply voltage VDD33 VDDA33 3 0 3 6 V Note 7 4 3 3V supply rise time tRT 0 400 μs See Figure 7 1 and Note 7 3 Voltage on USB and USB pins 0 3 5 5 V If any 3 3V sup...

Page 30: ...TTL Levels IS Type Input Buffer Low Input Level High Input Level Hysteresis VILI VIHI VHYSI 2 0 420 0 8 V V mV TTL Levels ICLK Input Buffer Low Input Level High Input Level Input Leakage VILCK VIHCK IIL 1 4 10 0 5 10 V V μA VIN 0 to VDD33 Input Leakage All I and IS buffers Low Input Leakage High Input Leakage IIL IIH 10 10 10 10 μA μA VIN 0 VIN VDD33 O12 Type Buffer Low Output Level High Output Le...

Page 31: ... Down Pull Up VOL VOH IOL PD PU VDD33 0 4 10 72 58 0 4 10 V V µA μA μA IOL 12mA VDD33 3 3V IOH 12mA VDD33 3 3V VIN 0 to VDD33 Note 7 5 IO U Note 7 6 I R Note 7 7 I O200 Integrated Power FET for GPIO8 GPIO9 GPIO10 GPIO11 High Output Current Mode Low Output Current Mode Note 7 8 On Resistance Note 7 8 Output Voltage Rise Time IOUT IOUT RDSON tDSON 200 100 2 1 800 mA mA Ω μs VdropFET 0 46V VdropFET 0...

Page 32: ... to the settings listed in Table 10 1 USB2250 50i 51 51i GPIO Usage ROM Rev 0x00 on page 35 Note 7 10 The 3 3V supply should be at least at 75 of its operating condition before the 1 8V supply is allowed to ramp up 7 4 Capacitance TA 25 C fc 1MHz VDD VDDP 1 8V Table 7 1 Pin Capacitance PARAMETER SYMBOL LIMITS UNIT TEST CONDITION MIN TYP MAX Clock Input Capacitance CXTAL 2 pF All pins except USB pi...

Page 33: ...scillator Clock Crystal Parallel Resonant Fundamental Mode 24 MHz 100ppm External Clock 50 Duty cycle 10 24 48 MHz 100ppm Jitter 100ps rms Figure 8 1 Typical Crystal Circuit Note CB equals total board trace capacitance Figure 8 2 Formula to Find Value of C1 and C2 XTAL1 CS1 CB CXTAL XTAL2 CS2 CB CXTAL C1 C2 CL 1Meg Crystal C1 CS1 x C2 CS2 C1 CS1 C2 CS2 CL ...

Page 34: ...MUST BE LOCA TED WITHIN THE ZONE INDICATE D TOP VIEW E1 4 D D1 E1 e 3 D 1 4 5 STD C OMPLIAN C E INTER PRET D IM ANDTO L PER ASMEY14 5 M 1994 DWG N UMBER PR IN T WITH SC ALE TO FIT DO N OTSC ALEDR AWIN G MATER IAL FINISH APPRO VED C HECKED D RAWN SC AL E SH EET R EV 80 ARKAY D RIVE H AU PPAUGE N Y 11788 U SA AN GULAR UN LESS O TH ER WISESPEC IFIED DIM EN SION S AR E INMILLIMETERS AN D TOLERANC ESAR...

Page 35: ... USB Vbus detect GPIO4 H SCL xD_ID Serial EEPROM clock output xD card detect GPIO5 H SDA Serial EEPROM data GPIO6 L SD_WP SD Write Protect GPIO7 H CF_DMACK TXD Compact Flash DMA acknowledge Transmit Port of Debugger GPIO8 L CRD_PWR0 Card Power Control GPIO9 L CRD_PWR1 Card Power Control GPIO10 L CRD_PWR2 Card Power Control GPIO11 L CRD_PWR3 Card Power Control GPIO12 L MS_INS Memory Stick Card Inse...

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