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Summary of Contents for STD 7000

Page 1: ...STD 7000 7801 808SA Processor Card USER S MANUAL ...

Page 2: ... e AU MPm 44444444M MP 4 4A4 Gq A 7801 808SA Processor Card USER S MANUAL 9 81 l e UOMC 4 iapapntiu n w li Ii n111 gin ...

Page 3: ...o o o ...

Page 4: ...ics STO Instruction Mnemonics Instruction Cross Reference Table SOSSA Instruction Set Interrupts PROGRAM INSTRUCTION TIMING Introduction WAIT States DMA Mode Instruction Timing Table Programmed Timing Example MEMORY AND I O MAPPING AND CONTROL Memory Addressing 12K Byte Onboard Memory Input Output Port Addressing Onboard Serial I O Lines PROGRAM AND HARDWARE DEBUGGING Microprocessor Logic State An...

Page 5: ...M capacity onboard 2716 type 3 State Address Data Control Buses Power on reset or pushbutton reset input Five interrupts Serial 1 0 lines All lC s socket ct Single 5V operation 7801 6_25 MHz crystal 320ns time states 7801 1 6_ 144MHz crystal 325 5ns time states External clock input option M RO INTRa IUMO WAITRO CNTRl IXT CLKI J1 INTIRRUPT AND SIR AL 0 ACCESS OCIISOR IOI5A DATA IUS ADORIIS loSTATI ...

Page 6: ...lOut Low Order Data Bus 10 06 InlOut High Order Ca a Bus BUS 11 01 InlOut Low Order Data Bus 12 OS InlOut High Order Cata Bus 13 DO InlOut Low Order Data Bus 14 04 InlOut High Order Ca a Bus 15 A7 Out Low Order Address Bus 16 A15 Out High Order A dress Bus 17 A6 Out Low Order Address Bus 18 Al Out High Order Ao lo lress Bus 19 AS Out Low Order Address Bus 20 A13 Out High Order AIjClress Bus ADDRES...

Page 7: ...e high impedance state except when addressed and directed to drive the data bus by the 7801 Note that the low order address bits AO A7 are multiplexed on the Data Bus AO A7 appear on 00 07 while MCSYNC is active The 7801 releases the Data Bus when BUSAK is active in response to BUSRQ as in DMA operations 3 Address Bus Pins 15 through 30 form a l6 bit 3 state address bus as shown in Figure 2 The 78...

Page 8: ...1edges INTRQ and rep1ace INTA e i MEMRQ RD to read i interrupt vector IINTRQ I 44 IN Maskable interrupt request I NTR WAITRQ 45 IN Synchronous processor ha 1t ROll NMIRQ 46 IN Nonmaskab1e interrupt request j TRAP 1 SYSRESET 47 OUT System power on and pushbutton RST reset one shot output I PBRESET I 48 IN Pushbutton reset input R CLOCK 49 OUT Time State tlock 1 2 crys ta 1 I CLOCK user optional fre...

Page 9: ...ow order address MCSYNC is equivalent to the 80SSA s ALE Address Latch Enable output signal STATUS 0 and STATUS 1 can be decoded externa 11 y to ident i fy the type of machine cycle in progress as shown in Figure 4 SEE NOTE I MACHINE CYCLE TYPE STATUS 0 STATUS I MEMRQ IORQi RDi It R t INTAKi 2 3 NOTES I 2 3 4 I Read instruction opcode 0 o I Read memory except opcode 1 Wr i te in memory Acknowledge...

Page 10: ...conds minimum after initial power on for stabilization of internal bias oscillators The 780l s power on reset one shot provides adequate stabilization delay only if Vcc risetime is less than 10 milliseconds Drive Capability and Loading The 780 IS STD BUS Edge Connector Pin List Figure 6 and Serial I O and Interrupt Socket Jl Figure 7 give input loading and output drive capability in LSTTL loads as...

Page 11: ... 20 19 50 5 A5 o A12 5 50 22 21 50 5 A4 A11 5 50 24 23 50 5 A3 A10 5 50 26 25 50 5 A2 A9 5 50 28 27 50 5 A1 A8 5 50 30 29 50 5 AO RD 5 50 32 31 5J 5 WR MEMRO 5 50 34 33 5 5 IORO MEMEX GROUND OUT 36 35 OUT IOEXP GROUND MCSYNC ALE 5 50 38 37 REFRESH STATUS O SOi 5 50 40 39 50 5 STATUS 1 S 1 BUSRO HOLD 5 42 41 50 5 BUSAK HLDAi INTRO I NTRi 5 44 43 50 5 INTAK INTAi NMIRO TRAPi 5 46 45 15 WAITAO READY ...

Page 12: ... OUT GROUND INTERRUPT 5 5 5 3 14 OUT GROUND SOD 50 4 13 OUT GROUND SID 5 5 12 OUT GROUND SPARE 6 11 OUT GROUND SPARE 7 10 OUT GROUND SPARE 8 9 OUT GROUND Low Level Active FIGURE 7 SERIAL I O INTERRUPT CONNECTOR PINOUT AND LOADING NOTE Pads are provided at spare pins for user connected signals PRO LOG CORPORATION A FORM NO 101905 ____ __ 45 l6 ml I 4T4 REV A SH r OF AlMA iLk It ...

Page 13: ...al or replace the crystal with a TTL compatible clock signal generated externally Details of this option are given in Append x A The frequency period characteristics of the crystal or external clock signal are shown in Figure 8 CRYSTAL OR I RESULTING i EXTERNAL CLOCK TIME STATE FREQUENCY PERIOD COMMENT I 6 250 MHz j 320 00 ns 7801 operating rate I I fastest allowable rate for 8085A with onboard cr...

Page 14: ...instruction Figure in response to INTRQ only FIGURE 9 BASIC 7801 OPERATIONS Note that the fa 110wi ng signa 1s a 11 have ident i ca I t imi ng character i st ics ADDRESS BUS A8 A 15 MEMRQ IORQ STATUS O STATUS 1 The waveforms on the following pages show timing measurements as a 5 1etter code as follows __ First letter is always T for Timing measurement Second letter is the abbreviation of the signa...

Page 15: ...ata time i 100 i setup i ns I j I H High state I I TRHDV Data hold time 0 I v Va lid I ns I I 1 iZ High TRlDZ Data bus dr ivers OFF high I I I j f I imEedance i impedance read mode after 0 i ns RD active I TRHAX Address hold time after RDi I t inact ive 135 i ns FIGURE 10 READ TIMING MEMORY FETCH INPUT PORT INTERRUPT INSTRUCTION NOTE In onboard memory read operations Section 6 the Data Bus does no...

Page 16: ...r f TD V J I _jwi Dx I 1 tr O A 7 0 v t 4 i i4 jr 0 J SYMBOL I PARAMETER MIN MAX UNITS j i I ns i TAVWH I Address va 1i d before wr i te I strobe WR r is i ng edge I625 TOVWH Data setup time and WR pulsewidth 400 1 ns l TWHDX Data and address hold time i 85 ns FIGURE 11 WR TE TIMING MEMORY AN OUTPUT PORT PRO LOG CORPORATION A FORM NO 101905 _ _ A4 EAM I REV A 4WM _MA MMU SHT 0 OF ...

Page 17: ... hold time after clock t transition in T2 for first a I WAIT state or in TH NOTE MEMRQ t and 10RQ timing is identical to Address Bus timing FIGURE 12 WAITRQ TIMING One WAIT state show l 1 1 J 1 v _ _ J I MAX I I I I I I UNITS ns ns ns I t I i I I o 01 WAIT REQUEST I The WAITRQ input allows the 7801 to enter the WAIT state in any memory I O or interrupt acknow edge cycle while a slow memory device ...

Page 18: ...at after BUSAK 50 ns is asserted allowing DMA operations TKHBV I 7801 resumes drive 6n the Address Data and Control I 50 I ns I Busses after BUSAK goes inactive NOTES 1 TH time states are clock periods during which the 7801 has relinquished the STO BUS allowing DMA operations to proceed with an alternate controller card Equivalent to 808SA Hold mode 2 The following Control Bus 1ines are floated wh...

Page 19: ...e 7801 may be needed for ribbon cable access depending on the connector and cable type used Environmental PARAMETER Free Air Ambient Operating Temperature Absolute Nonoperating Free Air Ambient Temperature Relative Humidity Noncondensing Absolute Nonoperating Relative Humidity Noncondcnsing MIN TYP o 25 40 5 o FIGURE 14 ENVIRONMENTAL SPEC1FtCATIONS MAX UNITS 55 Celsius 75 Celsius 95 100 PRO LOG CO...

Page 20: ... I OU H OUTPUT PORT I r __ _______ A _______ __L_J jl INST UCTION I IPA IN T_EJ RIR U_PT _____ I I_ I jirr i II T I _ __ e 2 JPN _ 43 t e _ I 1 2t e ROM 1 1 ll e I JP I STACK 1 MEMORY j t ADDRESS I INPUT PORT OIRECTI JI 1 ADDRESS RT 1 INOfRECT 1 1 1 ADDRESS 1514 13 12 10 9 8 7 6 5 4 2 1 O 401 01 5S 1 PROGRAM I I t 1 I1 I ADDRESS 1 COUNTER r 1 I t _ J I I I ___ _ J I I FIGURE 15 808SA PROGRAMMING M...

Page 21: ...outines and interrupts and can also be used to push and pull data in memory at high speed Subroutine return addresses are automatically stored on the stack when a jump to subroutine JS instruction is executed and are retrieved when return RT instruction is executed Interrupts in 808SA systems are generally treated as subroutine jumps All of the General Purpose Register Pairs and the Accumulator Fl...

Page 22: ... Pointer and the Program Counter allow addressing of 64K bytes of memory which can be any combination of ROM and RAM See Section 6 RAM is required for stack operations to allow the use of subroutines and interrupt The instruction set allows long direct addressing 16 bit memory address is part of the instruction immediate 8 bit or l6 bit data is part of the instruction and indirect 16 bit memory ad...

Page 23: ...time state clock frequencies Accordingly programmed timing such as count and test time delays witl require modification when running an 8080 or Z80 program on an 8085 and vice versa Note that only the 8085 instructions which are not part of the 8080 set are the LOA I and LOI A RIM and SIH serial I O and interrupt mask instructions S08SA vs 8085 Characteristics The 8085A differs from the 8085 in th...

Page 24: ... operated on Instruc tions without operands ignore the locator 3 The qualifier states the addressing mode or provides further qualifying information for compound instructions 4 The modifier carries detailed support informa tion labels conditions addressing and data The operator locator and qualifier letters are strung together to form the instruction mnemonic The modifier when needed stands alone ...

Page 25: ...E SET 1 0 STATE OF INDICATED FLAG CM COMPLEMENT ACCUMULATOR FLAGS PAIRED AJ ADJUST DECIMAL l RR ROTATE RIGHT GENERAL REGISTER PAIRS RL ROTATE LEFT DE 16 8IT DATA POINTERS r pS PUSH VIA STACK HL PL PULL VIA STACK P ANY REGISTER PAIR XC EXCHANGE R ANY SINGLE REGISTER I IP INPUT FROM PORT M MEMORY ADDRESSED INDIRECTLY MISCELLANEOUS OP OUTPUT TO PORT I INTERRUPTS EN ENABLE PC PROGRAM COUNTER OS DISABL...

Page 26: ...CLC CMC CMC CMA STC OAA CMA SEC AJA JP JP CX JMP JC JNC JZ JNZ CIt JP JM JPE JPO CIt CALL CC CNC CZ CNZ 1 1 JS JS CX ac CP CM CPE CPO Q Q RTS RTS CX RET RC RNC RC RNZ C RP RM RPE RPO JI JI xx RST Uti LOPt LXI B LXI O LXI H LXI SPJMP o PSP PSP PUSH S PUSH O POP H PUSH PSW PLP PLP POP B POP O POP H ac POP PSW C XDH XCP OE HL XCHG Go ac XTH XCPT HL XTHL 1 1 CIt INCP xx ICP INX B INX O INX H INX SP a ...

Page 27: ... register I indirect ICx 3C 04 OC 14 1C 24 2C 34 d z s p Increment register I DCI 30 05 00 15 10 25 20 35 d z s p Decrement register I ADA x 87 80 81 82 83 84 85 86 C6 c d z s p Add to A ACA x 8F 88 89 8A 88 8C 80 8E CE c d z s p Add to A W C SUA x 97 90 91 92 93 94 95 96 06 c d z s p Sub from A SCA x 9F 98 99 9A 98 9C 90 9E DE c d z s p Sub from A W C ANA I A7 AO A1 A2 A3 A4 AS A6 E6 C 0 01 z s p...

Page 28: ...on 3 bite Cx co 04 C4 F4 E1 DC CC FC EC Jump to Subroutine instructic RTS Cx C9 00 CO FO EO OS ca F8 E8 Return Irom Subroutine JPN HL E9 Jump Indirect n NMI 5 5 6 5 7 INTERRUPT 24 2C 34 3C RESTART AT SPECIFIED ADDRESS IN PAGE 00 JUMP TO INTERRUPT L 20V2S V30 V3SV RESTART ADDRESS INSTR MODIFIER 00 08 10 18 IN PAGE 00 RESTART AT JI XX C1 CF 07 OF E1 EF F7 FF SPECIFIED ADDRESS INTERRUPT AND SERIAL I ...

Page 29: ... at SP 2 PlP RTS line from SP Page rom SP 1 1 XCPT Hl L __t o SP H SP1 t lOPO Hl l ADR STPO HL H ADR 1 I I AUTOMATIC MEMORY ALLOCATION BY INSTRUCTION NOTE This table shows how memory is allocated automatically by the processor when certain instructions are executed For example the PLP instruction pulls a line address or low order register C E F or L increments the SP then pulls a page address or h...

Page 30: ...R A AFTER LOA I 5 S ___ 6 5 7 S ______ 1 ENI O DSI 0 ENABLEO 1 DISABLED REGISTER A BEFORE LOI A x 5 S 6 S ENABLE 0 DISABLE _ _ _ _ 7 5 1 MASK WRITE Ef JABLE FI GURE 22 BIT FUNCTIONS OF THE LOA I AND LOI A INSTRUCTIONS PRO LOG CORPORATION FORM NO 101905 444 41MUH hA1q 4 4 P I _ PM A _ iJ A REV Ar SHT 2 1 OF UM g 44 4 __MUCh a I 4 4 ...

Page 31: ...RQ is often used for catastrophic system events such as impending power failure but may be used for any interrupt function INTR 7 5 Jl pin 1 drives an edge sensitive latch in the 8085A Register I bit 4 resets this latch with the LOI A instruction Figure 22 INTR 7 51 INTR 6 5 JI pin 2 and INTR 5 5 Jl pin 3 are monitored and maskec by the I Register Bits 4 5 6 allow the program to monitor activity a...

Page 32: ...instruction and multiple responses to the same INTRQ signal cannot occur an input port bit or the Serial Input Jl pin 5 can be used to mon i tor INTRQ INTAK STD BUS pin 43 is active only in response to INTRQ as noted above Howeve the coincidence of status signals shown in Figure 4 can be detected outside the 7801 when needed to note the processor s response to any of the other interrupts This func...

Page 33: ...o 6 time states with specific activity occurring in each time state Although the number of time states and machine cycles vary among different types of instructionS they are precisely predictable for any given instruction Figure 27 Figure 25 is a timing diagram for the STAD STore Accumulator Direct instruction This instruction requires fourmachinecyc es MI through M4 with a total of 13 time states...

Page 34: ...T States Although the number of time states in any given machine cycle is fixed the user can insert one or more WAIT states in the cycle WAIT states are added by driving the 7801 l s WAITRQ line active during the T2 time state in the machine cycle see Section 3 for precise timing requirements for WAJTRQ The WAIT state is a do nothing time period that can be used to interface slow memories to the 7...

Page 35: ...nd of T2 If the WAITRQ line was active when sampled in T2 processor enters the AfT state instead of T3 If WAITRQ was inactive TW does not exist and the processor goes directly to T3 a In memory or input port read operations the processor reads the Data Bus at the lagging rising edge of the RD line during the second half of T3 b In memory or output port write operations the memory or port device la...

Page 36: ... older 8080 based systems note some 8085A instructions execute with fewer time states others with more time states than 8080 identical instruction functions Figure 27 uses the concept of Instruction Categories where similar instruction types are grouped without regard to specific instruction mnemonics For example the 49 load register with register instructions LOA A LOA B LOA C all have identical ...

Page 37: ...xcnange Top of Stacie with H L t III a 1 1 CTP Increment t Pair Count III II 5 3 HLO St l oad H L Oirect 1 1 t Jump IndiractJl oaa SP with HI 3 1 AOP Add Pair to H L g 3 2 IPA Read Input Port 3 2 OPA Write OutQut Port I 1 Interrupt EnaolelOiHble III INT Aead Interrupt MukS ana s tial In Z 1 1 Set Interrupt Muks and s nal Out J 2 1 1 Hl T Halt 1 1 NOP No Operation 00 only INSTRUCTION T1MING CAJ CUL...

Page 38: ...C CLC CMC CMC CMA STC OM CMA sec AJA JP JP CX JMP JC JNC JZ JNZ JP JM JPE JPO CALL CC CNe CZ CNZ III JS JS CX CPCM CPECPO Q Q ATS RTS CX RET RC RNC RC RNZ C RP RM RPE RPO D J I JI xx RST LPI LOP LXI e LXI O LXI H LXI SPJMP PSP PSP PUSH S PUSH O POP H PUSH PSW PLP Pt P POP e POP O POP H POP PSW C XDH XCP Oe HL XCHG Go XTH XCPT HL XTHL III t INCP xx ICP INX S INX O INX H INX SP a CTP OECP xx OCP oex...

Page 39: ...d the number of times each loop is executed loop iterations e If the program segment has more than one entrance or exit every combination of routes through the segment that are used by the program should be considered The following example shows how to compute execution times in a program segment The 808SA is programmed to generate a series of five short pulses at an output port bit line Determine...

Page 40: ... 3 20 Js i Low 1 1 FIGURE 30 SAMPLE TIMING CALCULATION The total execution time for the functions performed once outside the loop is 2 24 1 28 3 20 6 72 s One pass through the loop requires 1 28 3 20 2 24 3 20 1 28 3 20 14 40 s Five loop iterations requires 5 14 40 72 00 s however the JP ZO instruction requires only 2 24 us the fifth time instead of 3 20 us so the total time is corrected to 72 00 ...

Page 41: ...ypical m mory imple mentati on i s shown In Figure 32 12K Byte Onboard Memory The 780 1 ca rd as a comb i ned P i1 ROM and RAt1 memory on the ca rd wh i ch is 1arge enough to store tr e program3nd variable data required in many aoolications without the nee for aJ itiunal extdrllCil nemory cards The card is shipped ivith lK of RA L and sockets wh i cll a 11 ow the user to add up to 8K of EPROM or m...

Page 42: ...board memory to take control immediately after system reset recommended for most control applications ROM mapped into upper quadrant of memory allows user supplied RAM memory with post reset bootstrap at address 0000 required in many data processing and development system applications _ _ __ _ _ _ _ _ _ RAM addressing options allow for compatibility with various existing firmware packages and 8085...

Page 43: ...z o I c x I Z lJ J J c 0 o J c x Z 0 l X J c x U c I r I e i c c c c g c c f s o cccCC Ccc i i f i 0 i r r ...

Page 44: ...ing program generated data or control states Typical input and output port circuits are shown in Figure 33 Onboard 5erial I O Lines The 7801 provides one serial output line 500 and one serial input line 510 which are accessed at pins 4 and 5 respectively of the User Interface Connector J1 The serial I O 1ines are TTL compatible and suitable for serial communications between 7801 Processor cards in...

Page 45: ...S1 LIS 7 I t uGt 7 OS 51 51 13 74LS42 55 3 74l 42 c 05S C ss c SS 54 S I S4l 54 5 054 27 14 B S3 4 r5 4 053 IN 54 3 152 OUTsz Cl5Z _ I A SI Z t l t A SI 2 05 zc 3 t ISO i_ c D lOS SO FIGURE 33 TYPICAL INPUT OUTPUT PORT IMPLEMENTATION OUTPUT PORT r 07 7 L Sti 00 4 S 0 7 e 9 e 13 cr 1 E OC p I A r LRsr 0 0 INPUT PORT C7 Ii r Ul 1 7 0 O I l YP 0 12 Y O 1 07 7 L 1 S I 00 J F J rso o LATCHED GLITCH I F...

Page 46: ... logic low levels all of which are different but within specification This presents two problems the operator will find it difficult to identify the source of any given waveform on the scope display and in order to see a specific data segment on the Data Bus the operator wi ll find it necessary to synchronize the display with the processor s software program rather than with the voltage output of ...

Page 47: ... IfA UI IIlIl AOII A UI IIlIl lOll A UI IIlIl r N f f H Ta fa JI fa Tt n fa Tt n fa CD til OOW LM rtO MEII READ r 00 IN MEN UII f V1 0 rt CD CT r PC IIEM READ PC IIEM READ DIRECI r W MEN ADI J til 0 IN MEM IN MO iiiiifii lOAD rt n I MEM WRilE rO OU MEM Lilli f J til I MEM READ 3 til r IN MEM 01 rt f C MEM HEAD HI MEN WRIII UM OOrt IN MlM OUf NEM 0 e til n READ liE WRilE 0 n HII IN EM HIL OUI AlE C...

Page 48: ...rtable and clips onto the 8085A device on the 7801 el iminating the need for test probes and a lengthy test setup procedure I C rCU MACHINI CYCU ONi M1t 112 IU 1M MI AOIIII STATUS MIIil IDCUTI AOtt STATUS l1li111 AOIt STATUe AOIt STATUS l1li111 ADII STATUS TC TS M825 _ _ D SYSTEM ANALYZER 8085 MICROPROCESSOR o 0 o L r CD OA A StOIC aUf D t j to au o aa CYCLE COUNT I r STAfUS OA TA __ OOQOOOO JC 0 ...

Page 49: ...ices I O functions and BUS or logic signal analyzers require access to the system clock Connecting jumper A places the 3 125 MHz clock 7801 on STD BUS trace pin 49 CLOCK Note that the output driver for this signal is not floated during DMA operations Input an external clock can be used to drive the S085A s 01 input This should be a TTL compatible signal in the range of 1 to 6 MHz with 50 duty cycl...

Page 50: ... could be enabled on the same motherboard by employing memory and I O cards which regard MEMEX and 10EXP as high level active signals Thus a high level on these traces would select the alternate memory or I O bank while a low level selects the primary banks If the user wishes to implement alternate memory or I O banks open jumper trace G MEMEX or H IOEXP I on the 7801 This allows a peripheral card...

Page 51: ...c DOCUMENTATION c C PRO LOG CORPORATION A REV SHTLlS O p to3 A OF FORM NO 101905 ...

Page 52: ... 00 SID I t 11 1 1 7 t 1j q Ii 17 1 5 v J C J r q AC5 A i 2 2 A Z ADO j Tn M P I IO I1 WF AD ALE 1 _ lL DA L L II j 0 l4 L 3a L AIO IS A S I 5o l _I l 1f L VoW pE D fJ gr Jt 6 I A L r c T K h N E P i 07H 7 r tf C 5 j ME MOR I SV 5 I 1 00 11 l ao ri O J I WFFER 50 Sol INTA I RDll w a 1q Nt1t CLDCK 5 1 7 7 II S O 4 3 lTI TJ TA JS 1 1 0 1 tl 3 I M MRQ It 1 l GE r_ MC Y 1 Q SC PI Q SICNAT ON__ PHO LOG...

Page 53: ...OFIED 8 7 6 o 5 UV O d r REF c O A 5 o HOMO 4 4 3 3 2 ECHEMATIC NO 102745 H lRT oS Ue O 102141 1 1Jc 1 c l j o I UPDATE c45 E I I E _ T G I REV I ED PEl pcr eb 36 6 25 MHl f 17 IN 148 C I 16 15 I K Aw s F S 14 2K V W 5 1 R 13 K I TWC Rt Rl R R R 3 12 I r 1 4 51 11 6 10 1 oc o j7 w s t I 0 1 2 i l 7 h cL dv r 7 Ii v ITEM DESCRIPTlO Q iGIIAT Q PRO lOG CORPORATION o F O C c5 c c i __ e_ r RO_E O R IR...

Page 54: ...duction The Analyzer allows examination of the system address data and status during a user specified machine cycle at the desired Compare Address Observation of the system is possible at full system speed or by single step by instruction or machine cycle The possible display modes are dynamic mode in which the processor continues to run without analyzer interference and static mode in which the a...

Page 55: ...ed at Data Latch time and may be stepped through the program COMPARE STEP Switch Is only functional in stop mode and selects Stop on Address Compare and single Step on cycle or instruction o o MEMORY I O Switch Selects examination of data flow to from memory location defined by Page and Line 0 Address switches or I O device defined by the low order Line address switches HOLD REFRESH Switch Control...

Page 56: ...d to a Bus Request RUN STOP Indicates status of the Machine READY line RUN for program execution STOP for processor idle WAIT state CYCLE COUNT Machine cycle indicator showing the cycle of the instruction with which the displayed data is associated NOT FOUND Indicates that the selected machine cycle was not found ENABLED Indicates the Address Interrupt feature is enabled OUT OF RANGE Indicates a M...

Page 57: ...nd Cables Height 4 5 Height 1 125 Width 21 Width 2 5 Length 12 Length 4 5 Total product weight is less than 15 pounds OPERATING TEMPERATURE O C to 45 C M825 INCLUDES Analyzer Control Unit Plug in Buffer Module and Cable 40 Pin DIP Clip Connector Assembly 40 Pin Low Profile Connector Assembly Attache Case Two Copies of Operating Manual 4 0 125 TTL Loads 50 pf 0 25 TTL Loads 50 pf 1 6 TTL Loads 100 ...

Page 58: ... Zii2 i22 i i M4 ...

Page 59: ...USER S MANUAL 2411 Garden Road Monterey California 93940 Telephone 408 372 4593 TWX 910 360 7082 106903A 2K 9 81 o o o ...

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