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Panasonic JB-3300, Technical Manual

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Summary of Contents for JB-3300

Page 1: ...TechnicalGuide Portable Computer JB 3300 ae e Panasonic MatsushitaElectricTradingCo Ltd ...

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Page 3: ...ral of the integrated circuit chips used in this computer This guide limits repair procedures to replacement of subassemblies only A parts list containing part numbers for major subassemblies may be found in Section 1 item 8 Additionally a detailed parts list for each subassembly may be found at the end of each section Using the part numbers you can order the major subassemblies and some component...

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Page 5: ...er the computer Panasonic cannot be held responsible or liable for any damage caused or alleged to be caused We strongly suggest that for proper servicing the computer be returned to Panasonic Documentation Map For Specialists For Users JB 3300 Portable Computer User s Manual Service Manual For Field Service Unit Technical Guide Replacement For Repair Unit Repair JB 3300 Hard Disk Drive Floppy Ref...

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Page 7: ...ces cceee I 7 BLOCK DIAGRAM 2 ccc cc ccc cece cc ec ec cee eee eee ee eee eee eee eee e eee ee eect eee I 10 HARDWARE OUTLINE c ccc cc ce ccc cc cece ew cc eee eee cece ee eect eee weer ee eceee I 11 4 1 General Description em ee eee eee meee eee eee eee emcee eee essere cces I 11 4 2 Ventilation ecm meme e meee reece reece eee ene e reese sere seeeencns T 12 4 3 Memory Configuration weer cc ccc s...

Page 8: ... 2 ccc cc ecw ce cc wc ce cc we cme wre weer cece eee cece ees c erence esces II 5 MEMORY USAGE ccc cece cece cece ccc c cece cece cceaee eee eee eee ee ace II 7 4 1 Memory Map ccccccccccccccccsrcccccc ec r cece sec ec ccc resco secs oce TI 7 4 2 Display and Video RAM ConStruction 2 cece eee c cece cece nces TI 9 4 2 1 Basic Operation and Display ModeS cccccccceas TI 9 4 2 2 Video RAM Configuratio...

Page 9: ...ce eee ccc eee eee ee 4 4 Names and Functions of Signals cece ceeee cee cee cee 4 5 Notes Ce ec ee cee rece eer e ese ces cesvees cece ee eee cece cere cence 5 DISASSEMBLY PROCEDURE cc ecw ecco sees Cee ewe cece c rece cece ccc ee 5 1 Detaching Display from System Unit ce eee eee sees ose ees 5 2 Driver Disassemby Procedure eeeee eee ecw e ene rer 6 TROUBLESHOOTING 2cccee occ eeeeee wc eee ecw mem...

Page 10: ...were crew eees IV 7 4 5 HARD RESET ccc ccc ccc cere reece ce wee cee eee eee eee ete e eee ee ee sccens IV 11 4 6 SCANNING cecccccccccccv cc cccccecccccc cc ecec ccc e cece cere sccsccces IV 11 4 7 Repeat FUNCCION cece c ccc cece ccc ccc ccc cece cerns cece secs eeacesscceee IV 14 SELF TEST Jo cc eee ee ee wr wc cece ee ccc eer cee eee reece ee eee eee reso cee ne nccs IV 15 5 1 Self Test Start Co...

Page 11: ...ontrol CircuitS ccc ccc cence ccc ccc cece cc cc cece nceseces V 8 4 7 Secondary Control CircuitS cccwccccccccccccccccccccccccescccees V 9 4 8 Volume AGJUSKMENt ecw ecw ceec cece r cee c cers cccccrcccesceccccssnces V 10 TROUBLESHOOTING 2 cc ccc wc cc cc cw weer ee we cee re nec e reece ees e esse ence sccne V 11 5 1 NO OUtEPUE Lecce cer c creer eres cere nec rcrsccecsererevessssescsscsese V 12 5 ...

Page 12: ...eee c eee ceee cece eee rece ccee 6 3 Trouble Analysis Table wo ccc cc eww ee wwe ccc we cee ew cc ceee eee PREVENTIVE MAINTENANCE Lecce cece cece ccc cece cece eee eeseesece MEASUREMENT ITEMS FOR EACH MODEL eee eee wee eee c cee cecces ADJUSTMENTS AND VERIFICATIONS 2 2 2 ecw cccccvcecs ecm cere rc c ec ccccrcccess 9 1 Motor Speed Adjustment and Verification Index Period 9 2 Write Protect Verifica...

Page 13: ...e eo ow eon eee eae we eo em ewe aeons VI 19 REPLACEMENT PARTS LIST 2 ccc ccc cece ccc ccc cece ete cee enc ceceeceeees VI 20 REPLACEMENT PARTS LIST OF PCB Cece reer cece cere cece s cc eccccce VI 21 SCHEMATIC DIAGRAM 2 cece cece cece cc cece cece cece e eee e cece cecesees VI 23 CIRCUIT BOARD 2 cece ccc cece cece eee cece eee eee ence e eee s ee eeeee VI 25 BLOCK DIAGRAM 2 cece ccc ccc cece cece ...

Page 14: ...CE 2 2 cee ew ce ec cc ee cw eee ee ww ww we ew wee ew we eee te ee ee ne ene VII 9 4 1 Time Chart of Principal Operations 2 ecw cc ec ee ew ee ee ee we ees VII 9 4 2 Transmission Method 2 2 ce ce cee ee ee cw ee wee ee ee ew eee ee cee ene VII 16 4 3 General Flowchart of BaSic Operations cee wee cw eee eee ee VII 20 4 4 Main Command Flowchart cece ec ce ee ee ee et te eee eet eee ees VII 21 BASIC...

Page 15: ...cc ce ee ee ee ee ee ee ee ee ee ee ee ewe eee eee ee eee VII 54 PARTS LOCATION 2 22 cc www cw cw ce eee wee cc ec er were cere c weet were e ne ences cens VII 57 CIRCUIT DRAWING 2 cc ccc ecw cc ew ww ewww emcee emcee enews eee ete eee nescence VII 59 TROUBLESHOOTING 2 2 2 ccc ce ec ccc wc wee cece ee wr seen n ces e erence nese scsessces VII 73 TL 1L Outline e eee ccc cc ccc cw cc cee we ree ee e...

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Page 17: ...R NO DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit Il Plasma Display Unit IV Keyboard VV Power Supply Unit VI Floppy Disk Drive Vil Option Panasonic MatsushitaElecricTradingCoLid ...

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Page 19: ...ndard extendable to a total of 640K bytes Up to 512K bytes on main P C B 128K bytes optional 512 640K bytes inserting RAM board for PC or XT into option slots IBM XT Compatible IBM XT Compatible IBM XT Compatible IBM XT Compatible IBM XT Compatible ITBM XT Compatible Option slot is not occupied IBM XT Compatible Special for Plasma Panel 25 x 80 characters 400 x 640 pixels 16 x 8 char box or 25 x 4...

Page 20: ...ff of this switch 640 H x 400 V dots Dot pitch 0 3 H x 0 36 V mm Viewing are 192 H x 144 V mm Equivalent to 12 inch CRT Aspect Ratio 4 H 3 V Neon Orange NO Intensity Control for the Whole Screen FLoppy Disk Drive Type Number of Drives Capacity Access Time Average Track to Track Settling Time Average Latency 5 25 inch JA 551 035N SA455 Double Sided and Double Density 2 drives Floppy Disk Version or...

Page 21: ...nal Features National Versions 3 5 inch JU 104 1 drive 12 75 MB unformatted 10 MB formatted 85 ms 18 ms 8 3 ms 500 TPI Fourteen tracks are reserved in addition as alternate tracks 306 tracks IBM XT Compatible 84 keys IBM XT Compatible IBM XT Compatible Serial DIN connector IBM XT Compatible Cylinderical Sculpture Type Wider Return key Long Return key next to Ten key pad Lighted indicators on CAPS ...

Page 22: ... Yes 220 to 240 VAC 10 50 to 60 Hz or 110 to 120 VAC 10 50 to 60 Hz Switchable 220 VAC 1 5 A max 110 VAC 2 A max 160 W 5 VDC 10 4 A max 12 VDC 1 6 A max 12 VDC 0 26 A max 5 VDC 0 3 A max 205 VDC 0 15 A max 200 VDC O 1A max 12 VDC 0 08 A Power is supplied from the CPU board MS DOS Version 2 11 IBM XT Compatible Identical function call Tdentical values returned from Bios functions Same variable addr...

Page 23: ...e ROM BASIC is not available 430 mm 312 mm 155 mm Approx 11 5 kg Approx 11 5 kg No condensation No conden Operating Storage Temperature 5 C to 35 C 15 C to 50 C Humidity 35 to 80 RH 5 to 95 RH sation Temperature gradient 15 C hour 15 C hour Shock O 5G 40G Vibration 0 2G 1G except resonant frequency Height O to 2134 7000 ft ...

Page 24: ... Model Names West Germany JB 330 1ED 2 Great Britain JB 330 1EE 2 France JB 330 1EF 2 Sweden Finland JB 330 1ES 2 Holland JB 330 1EL 2 Australia JB 330 1EA 2 Hong Kong JB 330 1EH 2 1 1 FD version 5 HD version 2 256K byte memory 1 512K byte memory ...

Page 25: ...2 SYSTEM CONFIGURATION 256K bytes RAM on Board rr Pr 8087 Co Processor boom Ge Lo JB 3301 Floppy Disk Version JB 3305 Hard Disk Version Figure 2 1 System Configuration ...

Page 26: ...Appearance a JB 3301 Plasma Display Floppy Disk Drive Floppy Disk Drive Main Power Switch Keyboard Figure 2 2 ...

Page 27: ... b JB 3305 Plasma Display Floppy Disk Drive Hard Disk Drive Main Power Switch Keyboard Figure 2 3 ...

Page 28: ...ytes TIMER 8263 5 I O PORT i ee Floppy Disk Version K B I O Board 360K Bytes 360K Bytes _ _ 765A O i OQ 0 aJ Plasma Plasma Video Printer I F Parallel Port Display pend 640x400 I F Control Centronics For Printer c to V RAM COM I F RS232C 1 32K Bytes 8250 Serial Port BUS Option Bus Driver Connector x 2 See ae4 TOM Hard Disk Version Bytes HDD L i l Figure 3 1 Block Diagram 10 ...

Page 29: ...arking PLSMX T O Board PC board marking PLSY Power Supply Unit PSU Plasma Display Panel PDP Disk Drives 09 00 0 0 Two floppy disk drives Floppy disk version JB 3301 One floppy disk drive and one hard disk drive Hard disk version JB 3305 Figure 4 1 shows an internal view of the system unit Option Boards Hard Disk Controller l JB 3305 only ye a a FDD Zz Z O Board cpu Board Figure 4 1 Internal View I...

Page 30: ...on Diagram Memory Configuration Standard memory configuration for the computer is 256K bytes RAM 32K bytes video RAM and 16K bytes ROM This minimum standard memory is called the 256K bytes system Memory can be increased to 512K bytes with optional 256K RAM chips inserted in the IC sockets on the CPU board This is called the 512K bytes system Memory can be increased further to 640K bytes with an op...

Page 31: ...j co0o00 Li _ Loo Z CZ ee Byes A0000 LL __ WA Optional RAM 128K Bytes Optional 80000 RAM 384K Bytes RAM Expansion 256K Bytes 60000 40000 _ fp RAM RAM 20000 _ 256K Bytes 256K Bytes 00000 256K Byte System 512K Byte System Figure 4 3 System Memory Map I 13 ...

Page 32: ...ddress map Table 4 1 Input Output Address Map Hex Range Usage 000 OOF DMA chip 8237A 5 020 O21 Interrupt chip 8259A 040 043 Timer chip 8253 5 O60 063 PPI chip 8255A 5 O80 083 DMA page registers OAX NMI mask register 320 323 Hard disk 378 37F or Parallel port Centronics printer strap select 278 27F 3D0 3DF Display Color Graphics 3FO 3F7 Floppy disk 3F8 3FF or Serial port Asynchronous communications...

Page 33: ...hat corresponds to your problem by referring to the page numbers after each heading Important For the hard disk version execute the SHIP command before starting disassembly System Unit 1 Upper Case Assembly Power Supply Unit Speaker Disk Drive Unit Fan I O Board CPU Board ur ur un 1 Lo NO Figure 5 1 I 15 ...

Page 34: ...ve Keyboard D and all optional units away from working area Caution When removing the keyboard cable C hold the connector part and pull it toward you Do not pull the cord directly Step 2 Removing Rear Cover Rein fh H y SS Side View L il etTS Figure 5 3 1 Press down on thumbsets E of Rear Cover F and unlatch claws inside then lift Rear Cover F up from Plasma Display Unit G Do not use screwdriver to...

Page 35: ...heir bottoms can be Figure 5 4 released from System Unit Step 4 Removing Plasma Display Unit 1 Remove the four screws J on the softeners attached to either side of the plasma display signal 2 Remove the FG wires at both ends Cable of the softener by loosening screw K DC Signal Cable FG Cord 3 Remove the DC single cable and Keyboard Latch plasma signal cable Cable Step 5 Removing Upper Cover 1 Remo...

Page 36: ...Reinforcement Plates C 2 Remove PSU Shield Plate D we 3 Remove Reinforcement Plates c Figure 5 6 Step 3 Removing Floppy Disk Drive Unit 1 Disconnect Connectors E from Floppy Disk Drive Unit F 2 Remove mounting screws G 3 Slide Floppy Disk Drive Unit F to the right as indicated by arrow then lift it up from System Unit Top View Figure 5 7 Step 4 1 Remove Floppy Disk Drive Unit C Figure 5 8 I 18 ...

Page 37: ...it C 2 Remove Floppy Disk Drive Stay Support Plate I from Floppy Disk Drive Unit C 3 Insert the head protection sheets in the floppy disk drive C Head Protection Sheet Figure 5 12 Reverse steps for reassembly Caution The Drive with the terminator must be placed on the top when reassembling I 19 ...

Page 38: ...tors B 2 Remove mounting screw C 3 Remove Power Switch Plate D Note Before removing the switch plate lift it once to c prevent the claw from being broken Figure 5 9 Step 3 Removing Power Supply Unit 1 Remove screws E mounting system unit Disconnect connectors F from CPU and I O Boards 2 3 Remove Power Supply Unit 4 Remove Power Supply Board with Figure 5 10 Insulation Case Step 4 Removing Speaker ...

Page 39: ...ve Unit 2 Remove Floppy Disk Drive Unit see 5 2 Steps 1 through 4 3 Removing Power Supply Unit 3 Remove Power Supply Unit see 5 3 Steps 1 through 3 Step 2 Removing Handle Mount Assembly 1 Remove mounting screws B 2 Remove Handle Mount Assembly C Figure 5 13 Step 3 Removing Base Plate 1 Detach FG Cable D 2 Remove mounting screws E 3 Lift up Base Plate F Figure 5 14 I 21 ...

Page 40: ...ard B Note When removing I O Board B pull it from the I O con nector side left side of the bottom as the serial and parallel ports slightly lifted while the bottom is retained Reverse Steps for reassembly Important When reassembling the I O board be sure to properly connect the connectors between the I O board and the CPU board I 22 ...

Page 41: ...it see 5 3 Steps 2 through 3 4 Removing I O Board 4 Remove I O Board see 5 4 Steps 2 through 4 Step 2 Removing CPU Board 1 Disconnect Connector A from CPU Board D B D A L 2 Remove PCB support B and screws V A C retaining CPU Board D _ A 5 3 Lift up CPU Board D from Base Top View Figure 5 16 Unit Reverse Steps for reassembly Important When reassembling the I O board be sure to properly connect the ...

Page 42: ...ing iron during soldering Use a high insulation type soldering iron or if an ordinary soldering iron is used ground it to the chassis as shown in Figure 5 17 b Do not carry out soldering or replacement while the power is on c Be sure to attach the MOS IC to a black electroconductive sponge during storage or return shipment The MOS IC to be repaired should be attached to the electroconductive spong...

Page 43: ...PARTS LOCATION System Unit x_ Exproded View Figure 6 1 25 ...

Page 44: ...26 ...

Page 45: ... 8 GND 33 DACKZ 9 DB 4 34 FDOCS io GND 35 FocCcS ul DB 3 36 PSCcCS 12 DREQZ 37 PRTCS 13 08 2 38 CALDCS 14 GND 39 PCLK 15 DBI 40 RSCLK 16 GND 4ai Te 17 DBO 42 1RQ4 18 DO 43 1RQ6 19 DO6 44 1RQ7 20 D0OS5 45 POR 21 po4 46 GND 22 vos 471 GND 23 002 48 GND 24 DO 49 SPK 25 DOO 50 SECOND DRIVE Aol 1OCHCK BO G NO AQ2 E08 7 802 RESET AO0Q3 Eds 6 8B O3 5 Vv A004 EDB 5 BO4 1RQ 2 AOS EDB 4 BOS 3 Vv AO6 EDS8B 3...

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Page 47: ...2345 tt f 4cN2 CN19 70 9 few 1 CN20 PLASMA J2 3 cni2 Sole CNA 1 5V_ jie CE oe oa 2 200V CN26 f 3 195V a __ _ _ 1234 J2 ro J PLASMA J3 iPtoy N11 CN4 CNS 2 VR OUT Teac I o rd i CNB 2 1234 1234 a CN9be 2 J2 J2 1 ICN3 1 FDD PLSY CN20 a 1 PLSMX FDD PWB FDD PWB J2 FDD J JPKO2243B4 FPK FPK 1 12V Vi cno _T 00830 00834 TaT ov 3 _ 3 OV 4 5V ad KEYBOARD SPEAKER wot gscscct _ FOOD FDD 7 JA 551 035N JA 551 O35...

Page 48: ...TA 14 WRITE OATA 15 G N OD 16 G N O i7 READ DATA i8 READ OATA 19 G N O 20 G N O 1 1OCHCK 33 AB 14 2 GND 34 0ACK I 3 087 35 AB 13 4 RESET 36 0REQ 5 066 37 AB 12 61 5V 38 DACKO 7 O85 SS ABI 8 iRQ2 40 CLK 9 DB4 4 1 AB 10 10 42 1RQ7 it OBS 43 AB9 12 44 1RQ6 13 OB2 45 AB8 19 INTIO 46 1 RQ5 15 08 47 AB7 16 EXPODCS 48 1 RQ4 17 OBO 49 AB6E 18 RAMASEL 50 1RQ 3 i9 1OCHRDY 5 1 AB5 20 GND S2 0ACK3 21 AEN 53 A...

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Page 50: ... 3 AC N 3 AC iN 3 AC N a a BRIGHTNESS J2 Jf2345e7 i2sase7a JI B CONTROL 12V Ov i Ji ah 4 putat J2 Jt A J1 B ales I PLASMA J it243 _ DETECTOR FDD PWB HDD FPK 0083 AN L FDD JA 551 O35N PLSY CN1 PLSMX 1 PLSMX CN7 GND N QUIN C DETECT OPEN PLSMX CN8 Ht 12v 2 GND FAN 2 FDD J2 HDD J8 1 Figure 7 2 PLSY CN25 it 3Vv_ 2 GND PLASMA PLSY CNI9 at 1 J1 A 5V V PLASMA Ji PLASMA J2 1 5V 2 200V 3 195V PLASMA J3 i 5V...

Page 51: ...09720B1 Front Panel FHD 1 15 YJJDA01140B4 Ac Cord 1 16 YJJ7002050B4 1 Caution Lever Ref No Parts No Parts Name Description ae Remarks 17 YJJ2P09111B2 Insulation Case 1 18 YJJ7T11870B4 Lavel 1 19 YJJ2H09101B2 PSU Shield Plate 1 20 YJJ3B091 20B3 Roinforcement Plate 1 21 YJJ2S09090B2 Support Plate 7 4 22 YJJ7T05950B4 Earth Lavel 1 23 YJJ2T09201B1 Base Plate 1 24 YJJ2J09190B4 Plate Support 4 25 YJJ2J1...

Page 52: ... 1 43 YJJDKO2611B4 FDD Signal Cable 1 44 YJJ6GO08691D3 PR CN Plate 1 PLSY 45 YJJ7T13280B4 Main Lavel 1 A YJJ2006590A4 Plasma Display Unit 1 B YJJ2007100A4 Keyboard Unit G 1 YJJ2006600A4 SW Fin 1 YJJ2007130A4 UK 1 YJJ2007140A4 F 1 YJJ2007150A4 NE HK FA AU 1 C YJJUSO3280B4 Power Supply Unit 1 D YJJA 551 035 Floppy Disk Drive 1 E YJJU 104 Hard Disk Drive 1 F YJJ4039430A4 PLSY P C B Ass y 1 G YJJ30064...

Page 53: ...he defective power supply unit must be sent back to our factory r WARNING This computer uses some special parts for safety and protection They are marked by the international safety mark A in drawings and replacement parts lists Always use Matsushita s parts to avoid unpredictable damages X ray exposure electrical shock burning etc Note The diagnostic program consists of several units Diagnose eac...

Page 54: ... o Read Write check disks Scratch disks 2 or more Note The plug for a loop back test must be wired as follows Panasonic Part No RHC 515 Connect Pin 2 and Pin 3 Connect Pin 4 Pin 5 and Pin 8 Connect Pin 6 Pin 20 and Pin 22 Note A scratch disk is a blank disk or one that doesn t contain any files that you will need It must be formatted for DOS I 38 ...

Page 55: ...bleshooting Visual check item Troubleshooting section OOOO Reference troubleshooting block Figure 9 1 o Block flow chart No 1 Unstartable After Power ON Yes X 1J3 40 5 5 Ve GB DC Power Unit Section or block item Measurement or Signal name Check pin name or IC pin number X Y PLSMX PLSY Possible error unit OOOOO Reference explanation drawing table and timing chart These are listed in that seguence i...

Page 56: ...keys KBDATA KBCLK KBDATA KBCLK Visual check item Connector Typical waveforms to be measured Waveform diagram or condition QOOYVOO Possible error part or block Figure 9 3 o Block flow chart No 3 ALE Oscilloscope 2 ALE synchronization ALE G Preparation item 2 Connector to the other page 2 2 is an item number Figure 9 4 I 40 ...

Page 57: ...rror Message No Floppy Disk Error Message Printer Error Message No Communication Error Message No Yes Yes Yes YOS ge Yes Yes Yes Figure 9 5 1 2 System Unstartable Section 1 PDP Controller Section 2 1 Keyboard Section 3 1 RAM Read Write Section 5 1 15 2 Hard Disk Section 6 1 6 2 Floppy Disk Section 7 1 Printer Section 8 Serial Port Section 9 ...

Page 58: ...K DRIVE 5 PARALLEL PORT 6 SERIAL PORT 8 HARD DISK DRIVE 9 LOCAL SPEAKER MPU System Section 4 RAM Read Write Section 5 1 5 2 Keyboard Section 3 2 3 3 PDP Controller Section 2 2 Floppy Disk Section 7 2 Printer Section 8 Serial Port Section 9 Hard Disk Drive Section 6 1 6 2 Local Speaker Section 10 Figure 9 5 2 2 42 ...

Page 59: ...40 12 V 10 Y CN 3 4 5 V 5 Y CN 2 No System Reset 1 Circuit X 2N 10 II 5 2 a Yes 5 V t RESET Ly Dace we t 400 ms 1 3 s is No Clock Generator CLK 4 77M i OK 8284A X 2N 8 II 5 2 b CLK 69n u PDP Controller Section 2 1 Wait State Generator 8284A we N MPU Bus Controller c we 8288 XMEMR Figure 9 6 1 2 ...

Page 60: ...M Chip Select Circuit II 5 5 e Replace BIOS ROM II 5 11 __ Refresh Timer Circuit 8253 5 LL we DMA Circuit 8237A 5 15us r II 5 6 DREQO C DACKO U a No ge RAM Circuit X 4P 15 It 5 5 No Interrupt Controller 8259A X 1J 18 II 5 8 No p NMI Circuit X 1J 17 II 5 4 MPU Data Bus II 5 3 to 4 Figure 9 6 2 2 ...

Page 61: ... OK CPUADR RAS Signal OK CAS Signal OK No _ Memory Address Decoder X 8C 4 II 5 5 a I No PDP Controller WAIT Circuit X 7G 13 II 5 9 g I No _ PDPC video RAM X L2M 6 Access Timing Circuit II 5 9 h I Oscilloscope CPUADR Synchronization X 12M 6 No X pas No y PDPC RAS CAS Timing Circuit II 5 9 h Figure 9 7 1 2 45 ...

Page 62: ... to 14 No X 9D2 to 9 No X 9D11 to 18 PDPC Video RAM Address Controller PDPC Video RAM Data Bus PDPC MPU Data Bus II 5 9 7 __ II 5 9 k It 5 9 k No X 3C 11 39 93 HSYNC STA pine 17 58u No 18 61 m CRTC CLK OK we Video RAM Chip II 5 9 k Figure 9 7 2 2 46 Ir 5 9 h PFPC CRTC Clock Control Circuit _ PDPC CRTC Parameter Converter CRTC LSI II 5 9 e i ...

Page 63: ... Switch wi Cable Connector ei PDPC Display Mode Register II 5 9 c PDPC CRTC Parameter Signal OK 39 93u HS Yes 10 85u 18 61 m VS 119 8y co No 5 V 195 V 200 V PDP DC Power Connector Signal DC Cable OK Converter CRTC LSI HSYNC VSYNC Circuit II 5 9 e i p pei V Power Supply Unit Check PDP Signal Cable PDP DC Cable Plasma Display Panel Figure 9 8 1 2 47 ...

Page 64: ...X 10D 2 3 5 6 10 11 13 14 Yes X 9H 2 5 6 9 12 15 16 19 DISP DLY No X 12K 11 CRTC Control Signal Converter CRTC LSI II 5 9 p PDPC Basic Timing Generator II 5 9 h PDPC Display Mode Register II 5 9 c PDPC VIDEO DATA Control Circuit II 5 9 0 PDPC CHG Font Latch Circuit II 5 9 2 PDPC Video RAM Address Controller II 5 9 ee PDPC Video RAM Data Bus PDPC RAS CAS Timing Circuit II 5 9 k Figure 9 8 2 2 II 5 ...

Page 65: ...it aracte Ir 5 9 28 No I erticalk ves PDPC VIDEO DATA 4 Line of All a Control Circuit Character II 5 9 0 No Specific Yes C bot and Specific w PDPC Video RAM P artoan 2 Il 5 9 k No I PDPC Video RAM cI Specific Yes Address Controller Row CRTC II 5 9 3 No Nf specifi ves PDPC Video RAM mela s mj Address Controller a CRTC It 5 9 3 No III Plasma Display Unit Figure 9 9 ...

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Page 67: ...ay PDPC Display Mode Register 80x25 Display PDPC Display Mode Register 320x200 Graphics 640x200 Graphics PDPC Display Mode Register PDPC Display Mode Register No 640x400 Graphics s Graphic CI Pattern Error S PDPC Display Mode Register screen Paging Paging Error No Is CRTC CLK Signal OK No PDPC Basic Timing Generator PDPC Video RAM Address Controlier Figure 9 10 51 ...

Page 68: ...ON 5 VDC Power on Self Diagnosis Error II 5 10 Signal OK SS Replace ICP C KBCLK S KBDATA Keyboard Inter face 8255 5 ML No a X CN4 5 No a KECLK HH 240 ms KBDATA Max 10 ms tae No Signal OK KBDATA No Key Inputs Available Missed Key Input Figure 9 11 53 1 2 ...

Page 69: ...X 1J 18 INTR Signal OK KBDATA 5 V Level OK Keyboard Section No Cable or Connector ew Reset Circuit mi IV Keyboard receLIUUUUUUUUU ST wo on oO mye ton wae ton to Keyboard Interface Interrupt Controller 8259A X 2C 3 to 13 Keyboard Interface Check MPU Data Bus PPI 8255 5 Il 5 3 to 10 L Figure 9 11 2 2 ...

Page 70: ...e Check Key Switch Missed No NO 3 2 KBCLK L LI sT oOo ton or wpe to wpe Ho or t KBCLK KBDATA KBDATA Is IRQ1 Signal No _ Keyboard Interface OK II 5 10 Yes L Are KDB7 to No Serial Parallel 0 Signal 1 Converter OK II 5 10 Yes LL Check PPI 8255 5 II 5 10 t__ Figure 9 12 ...

Page 71: ...Error ROM CHECKSUM Error Yes Replace BIOS ROM Yes CLK Si System Clock Ss igna Generator 8284A X 4F 9 ei PITC 8253 Yes DMAC Error No DREQO Signal PITC 8253 OK ea PITC 8237A 5 Yes m1 PPI 8255 5 Yes PIC Error mi PIC 8259A Figure 9 13 1 2 56 ...

Page 72: ...No Figure 9 13 2 2 TIT 57 ...

Page 73: ...Bit RAM Oscilloscope ASEL RAMASEL Synchronization No X 6L 3 RAM Circuit RAS X 5M 6 8 CAS X 4P 15 14 CAS Oscilloscope CAS Synchronization X 4Pp 15 14 PDPC Video RAM Data Bus MPU Data Bus RAM Address MPX Circuit e RAM Chips Figure 9 14 1 2 I 58 II 5 6 II 5 9 k I TI 5 9 k L II 5 6 II 5 6 ...

Page 74: ... Two or More Bits 6L 3 RAM Circuit RAM Circuit LS31 X 30 2 No X 7B 3 pe RAM Circuit LSO8 Note Address and Data table for indexing vb Don 2 7N_ vo3 vos 6p D7 vp2 ws 2 62 2 79 vor vod oR DD 7K voO Address OOQOOH to 3FFFFH Figure 9 14 2 2 59 II 5 6 l II 5 6 II 5 6 applicable memory vo D sn oN vD3 vpoe 8p 9P__ vp2 vos Pp 89 2 99 v1 v4 8R 9R vD0 Address 40000H to 7FFFFH ...

Page 75: ...ess Decoder FD Control Command Register II 5 10 e No 1 I O Address Decoder II 5 7 CLK Y 9G 19 4 MHz WCLK Y 9G 21 500 kHz Are CLK WCLK No Signals OK Yes Replace 16 MHz OSC VFO SED9420C Circuit II 5 10 e 1s N egnal o FDC uPD765AC oxy 96 18 II 5 10 e Yes Interrupt Control Circuit II 5 10 e Figure 9 15 1 2 ...

Page 76: ...MAC 8237A 5 Circuit DACK Gate Circuit Error Ss DMAGATE No Signal OK Y 4F 15 Yes Is No DC DRQ Signal OK Y 9G 14 Yes Is No DREQ2 Signal OK J Y 4F 11 Yes Is DACK2 Signal V2 2 OK 12F 6 Yes Is FDC DACK No Input Y 9G 15 Is TC Signal He Ov oe Yes DMAC Circuit TC Gate Circuit FDC uPD765AC Data Bus Figure 9 15 2 2 ...

Page 77: ...Power ON Reset 12D 2 Circuit IT 5 10 e we No VFO SED9420C CLK WCLK wm Circuit IIT 5 10 e IIT 5 10 e OK Yes Is MOTOR O No Signal Low Y 5F 6 Yes Is No FD Control Command DRIVE SEL1 e Register Low Y 12E 8 Yes Is No INDEX Signal Replace FDD Unit OK Y 1LOE 11 Yes Figure 9 16 1 2 ...

Page 78: ... Signal OK Yes Is WRITE DATA Signal OK Yes No ew Replace FDD Unit RDDATA No e FDC uPD765AC SYNC No CNTL CNTL 2 4 Vv OT CNTL VFO SED9420C we Circuit Y 9G 23 Y 9G 24 Il 5 10 e No Y 11C 2 wet FDC UPD765AC Y 5F 2 Y 12D 3 Il 5 10 e No FDC uPD765AC we Pre Compe Circuit Y 12D 11 II 5 10 e w Replace FDD Unit Figure 9 16 2 2 ...

Page 79: ...Print or Status Error Printer Select Switch OK Yes Is BUSY Signal OK Yes Is BUSY Signa OK Yes Is No_ TROBE Signal Yes Is ACK Signal OK Yes No Set Printer ei Select Switch BUSY Holds 0 Y 8E 17 ERROR Holds OM Check Printer Y 6E 15 No 8C 3 Printer Interface Il 5 10 b Figure 9 17 1 2 ...

Page 80: ...Character Missed Character Is Printer Self Check OK Signals OK Yes Correct Yes No Y 6E 15 2lus STROBE eens Y 8C 3 Y 8E 17 BUSY ACK is No Data Code en Y 5E _ Printer Interface II 5 10 b Check Printer Figure 9 17 2 2 ...

Page 81: ...0 EIA Driver 75154 EIA Receiver ge RS 232C Interface DC Power No 12 V OK Y 4GA 5 Yes 12 v 5 Is RSCLK Signal 2 OK Y 7G 16 1 843 MHz Yes Select No Switch OK Yes Are DTR RTS No _ 5 a Signal OK 4GA 6 7 Yes Are CTS DSR No _ Signal OK Y 5G 5 6 Yes Is IRQ4 Signal No OK Y 6D 6 Yes Interrupt Controller Figure 9 18 1 2 II 5 9 h II 5 10 d II 5 8 ...

Page 82: ...DPC Basic Timing Yes RSCLK Signal Generator ea Yes Are Cre No Y 4GA 6 7 Yes No Y 5G 5 6 No y Y 5G 4 Y 6G6 4 No Y 1E 6 Y 4GB 7 Y 5G 7 Yes FIA Driver No EIA Driver Receiver Receiver P 75150 75154 OK II 5 10 da Yes oN N RSCCS Signal 2 mi I O Address Decoder OK Y 7G 14 Il 5 7 Yes i UART 8250 Data Bus II 5 10 d Figure 9 18 2 2 ...

Page 83: ...Unusual Beep SPKOUT Yes Signal OK iReplace Speaker Unit X 4E 3 SPKFRQ Signal OK SPKDATA Yes Signal OK Speaker Drive Circuit X 4E 1 II 5 10 c No C Sionaton Yes i ge i PITC 8253 5 gn X 4F 16 II 5 11 No cc ee PPI 8255 5 II 5 10 c Figure 9 19 ...

Page 84: ...OM When an error is detected a warning sound is generated or a warning message is displayed on the screen The power on time self diagnosis flow is shown in Figure 9 20 The RAM read write check is not carried out only if the ESC key on the keyboard is pressed at the power on time Table 9 1 lists self diagnostic error messages I 69 ...

Page 85: ...mory of First 16K Bytes r No Check Memory Size Max 640K Bytes Function Check of Interrupt Controller Yes Error No Halt System Initialize PDP Controller Check Memory of Video RAM Yes Error No Check Video Interface Error Sound Local B Speaker 14 SSP Check Keyboard Figure 9 20 Se1f Diagnosis Flow 1 2 ...

Page 86: ... Error Message 2 Print Error Message 3 Check Floppy Disk Controller tS No r Check Printer Interface Check Communication Interface RS 232C Print Error F1 Key Pepressed 2 Be Yes Go to Boot Strap Loader Print Error Message 4 J Print Error Message 5 _J Print Error Message 6 Message 7 eee eee Message Error FLOPPY DISK COMMUNI CATION Figure 9 20 Self Diagnosis Flow 2 2 ...

Page 87: ... a Hand Disk Controller Failed 4 FLOPPY DISK ERROR _ Floppy Disk Controller Failed 5 PRINTER ERROR _ Printer Interface Failed 6 COMMUNICATION _ _ Communication Interface Failed ERROR 7 PRESS Fl KEY 2 short Beep Unknown error occurred 3 short 3 long 3 short Beep SOS iif VIDEO RAM Failed HSYNC Signal Failed VSYNC Signal Failed Halt System BIOS ROM Failed Check Sum Error DMAC Failed Refresh Timer Fai...

Page 88: ...rallel port printer Serial port RS 232C Floppy disk Hard disk Local speaker OMAN A OB WD FE The program can be started once the MS DOS system disk is loaded At the end of the diagnosis the DOS must be loaded again Preparation Connection should be made as shown in the figure below tN see ESSEEN ERTS A Cs SDSSLES 1 JB 3300 4 Printer ex KX P1091 2 Diagnostic Disk 5 Printer Cable G Scratch Disks 6 RS ...

Page 89: ...puter s Enter new time _ logic unit The system unit should be serviced 3 Press key A _ 4 Type ENTER THE TYPE OF Be sure to select the correct KEYBOARD number corresponding to your fa a g 1 USA 2 SWEDEN countrys keyboard as displayed 3 DENMARK on the above screen If you make an incorrect country key board Selection the screen will display different character during the keyboard test DO YOU WANT A I...

Page 90: ...en devices and then returns to the diagnostic menu Press 2 and to begin the automatic test CHANGE MENU The program must know what devices are installed in your system to test them To obtain a menu of the installed devices select CHANGE MENU by pressing 3 and ERROR LISTING To obtain the results of the diagnosis select ERROR LISTING from the diagnostic menu by pressing 4 and EXIT When you have run a...

Page 91: ... below When you have finished press 16 and to return to the diagnostic menu To terminate the test before it is completed press the Break key while holding down the Cntrl key The screen should return to the diagnos tic menu 1 MAIN BOARD Test 1 Type MAIN BOARD TEST into SYSTEM Test complete DEVICES MENU P Press any key to continue If any errors are found on the board the screen will display MAIN BOA...

Page 92: ...ar the return key or any of the letter number or punctuation mark keys Caps lock shift keys and similar keys will not work as responses to this prompt 2 MEMORY Test If an error is found you will 1 Type MEMORY TEST see a message like this This test takes up to 2 minutes Please stand by Test Address xxxxx Data xx xx complete Press any key to Write data continue _ Read data If there is a problem in t...

Page 93: ...ld down the block representing that key should change to display the character on the key in reverse video e g When the key is released the character should be displayed normally e g A If the display does not look like this press n and 4 Check the keyboard cord If the cord connection is loose plug the cord in firmly and run the keyboard test again If the display is still not correct the keyboard s...

Page 94: ...ess the number 6 GRAPHICS MODE of the first test you wish to 640 x 200 run and After each test 7 GRAPHICS MODE the screen will return to the 640 x 400 Original display You can then 8 PAGE CHANGE TEST run the next test 9 EXIT When you have run all the tests SELECT OPTIONS you want press 9 and to _ return to the SELECT DEVICES menu The following sections show the screen display and the action requir...

Page 95: ... Error messages are described in Error Messages Section 2 Press any key to return to the menu 6 SERIAL PORT Test 1 Type 6 SERIAL PORT TEST into SYSTEM DEVICES MENU Attach the loop back plug to the connector Press any key when ready __ 2 Attach the loop Press any key to The diagnostic program will back plug continue _ perform the test you have selected and print diagnostic Press any key messages if...

Page 96: ... EXIT SELECT OPTIONS __ 2 Enter the k k k WARNING A scratch disk is a blank disk number of the Disk will be over or one that doesn t contain test you want written any files It must be format to perform ted for the DOS Insert scratch disk in drive A and press any key when ready 3 Insert the The diagnostic program will scratch disk and press any key perform the test you have selected and print diagn...

Page 97: ... you do not want press N and Then the diagnostic program perform You will see the following message RANDOM SEEK TEST The diagnostic program perform the random seek test DISK WRITE TEST The diagnostic program perform the writing test on max cylinder The diagnostic program print diagnostic messages if there are errors as in following examples kk KK FRROR RECORD NOT FOUND Command 82 H 01 C 205 S O1 A...

Page 98: ...two parts as shown in the following examples RECORD NOT FOUND Command 82 H 01 C 205 S O1 Address 100 Wt DB Rd D6 1 RECORD NOT FOUND Type of error 2 Command 82 Head O1 Cylinder 205 Sector O01 Error mode and location Hard Disk Operation Section ROM Error During Basic Assurance Test ROM ERROR HDC ROM Sum No _ HDC BIOS ROM OK 12764 YES Host Interface Section I 83 ...

Page 99: ...ROR NO Drive LED OK YES Power supply unit Hard Disk Drive Unit 1 S N Interface cable OK YES Drive Ready YES Is NO NO Connect inter face Cable Buffer Ram R W OK YES Is NO Host Interface Section rackO Signal OK YES Hard Disk Drive Unit I 84 Drive Interface Section ...

Page 100: ... Is RDATA Signal OK YES Are tep Dir Signal OK YES Is Write Gate Signal OK YES Is WDATA Signa OK YES NO NO Power Supply Unit NO LOW NO NO NO NO NO NO Clock Generator 10000 kHz Hard Disk Drive Unit Drive Interface Section Hard Disk Drive Unit Drive Interface Section Drive Interface Section Drive Interface Section I 85 1 Exchange Hard Disk Drive ...

Page 101: ...r Print Outs 1 Type 9 LOCAL SPEAKER TEST You should hear a series of into SYSTEM ascending tones from the local DEVICES MENU speaker If you don t hear any tones the system unit should be serviced 2 Press any key to continue _ 3 Press any key to return to the menu I 86 ...

Page 102: ...orrect press N and RETURN Figure 9 22 Keyboard Test Preneeachhey for character replacement leaei2zes4s567898 ms 3747 QWERTYUIOPT Jj 789 97 6c ASDFGHIAI KL 7 r456 7 8TtNZXCVBENM 4YFtX 123 9 a _ c r If correct press Y and RETURN If not correct press N and RETURN L J Figure 9 23 Keyboard Test I 87 ...

Page 103: ... Eig Soin Hw cel pp Os OS em 53 27 Cate egee oO Pe RR 2 Cr NOee SOR UA erm py TSB sr Eisin Tae 7 40 hey E th Zt Meer sia tele OD BIR s eeool ooo CHARACTER SET TEST Figure 9 24 Attributes Test thi cone ee comm tam cone anes ebb Ob eet tl THIS eee oo LINE a PaLM Mes THI oo ee been ad eae aee THIS LINE IS HIGH INTENSITY VIDEO THIS LINE S NORMAL V LOE ATT 2LITE w otoe TES ...

Page 104: ... peo i FE en 0s eek OW 8 eee ee er Ff I o 8 mle EL A Te ek ee fee ee sos aos 2 Je ee Seleles FE at ale we ere ene er re ye oele e BEE aT 8 le ae OW LL ees eet one et I LAT ee eee PE at 6s ee Ow oe feb el ea oad erUe T meters we oon eee ee OW He eeOf ke ote OLet e Ve eee EE a a WIN hese Fe e em e Ea one 6 ee TI shes veg Re meee al le ek te Ag tle UF ejer ey Ve gt mee ee e ete pe 8 6 UB afer oe Vag ...

Page 105: ...n cel LTBI Is this correct CYAN Figure 9 28 320x200 Graphic Display Test ws aa ne ay _ ae wf a mm mS 4 ra ra _ os Me f a om er a ff XL an vf a a f Nee _ Lf Lh N N re a Is this correct Y N oe Figure 9 29 640x200 Graphic Display Test I 90 ...

Page 106: ...b b ba bbose HHHBADHBE OBA OOH Ahhh hb hhh heehee HEH HOH HB HDB BBB bbb hb bbb bobo bb hab ob OH HHH BBG H EBB HOB BRB R BHABHA bbe oe hbase bees HOB BOB OBE BRB ORB OE BBB BBG bbb bbb be eeeos HUY BBHBOEHE BEBE HHO E bbb bebo bbbobebobeeeg HE BHO R BBB B BBO OBB OBR bebo hb ob bbe eee BOD HE BH OOOO BARE BB BO BRB hb bha bbe bbas HHH EBBBHAGHBOEOHBBBBBOOHHEEab bbb beh eee bobo BUBEOBEOHEEOB HH A...

Page 107: ...N IT sthcoefanigkimroarerst 3 oS SPEGECTEPGHI IKLMNOFORSTIUVUWUMYSONI aterdetanigk lmneearetu ARCTEFGHIIKLMANOFORSTUULUIOY ION 37 _ ancdetaki gk linnmoparsetuy 3 RBRECTEFGHI JKLMNOPAPSTUUWZYZOINI7_ epcdetahisk limnoparstuvu WRF K AOL ESASECES Ss 8 SMRAECIEFGHI IKLMNGOPORSTUUWe2D IC atrdetahi gk imnorarst uve THIS LINE ITS NORMAL PRINTING THIITSS Wiiltrwe Is EMP ANDe Do Fe TR Tes THIS LIME JS COMPR...

Page 108: ... details on the testing of each device Note that the screen display may differ slightly because you don t need to press any keys to move from one test to the next To terminate the automatic test before it is completed press the Break key while holding down the Cntrl key The screen should return to the diagnostic menu If not you may first have to respond to the current message on the screen When th...

Page 109: ...ELETE 1 Press Enter D elete or A dd 2 Press a ENTER THE NUMBER OF If your system does not have THE DEVICE TO BE all the devices listed press DELETED _ d 3 Press number Key in the number of the key device on the list that is not in your system and press ADD 1 Press Enter D elete or A dd 2 Press a ENTER THE NUMBER OF If the list does not contain THE DEVICE TO BE all the devices including op ADDED ti...

Page 110: ...NG NUMBER DEVICE 7 FLOPPY DISK Press any key to continue or ESC to end _ EXECUTE ERROR 00001 00000 Number of program executions and errors are also included in the above message when a problem occurs If you want to see the details of Error Listing press any key The details of Error Listing will be displayed on the screen However the contents may differ depending on the cause of the problem If you ...

Page 111: ...ot counting correctly DMAC FAILED The memory refresh DMA failed PPI FAILED The PPI 8255 5 did not read write correctly PIC FAILED An unexpected interrupt occurred in the inter rupt controller or an interrupt was not correctly checked 232C FAILED The UART 8250 control read write is not possible PRINTER I F FAILED Signals to the printer interface were not returned correctly CRTC FAILED CRTC control ...

Page 112: ...ne status Rev data xx Statusl xx Meanin Bit Status2 xx J D7 D6 D5 D4 D3 D2 Di DO or TIME OUT 1 STATUS Sd data xx Trans Shift Register Rev data xx 1s empty Statusl xx Status2 xx Trans Holding Register is empty Break detect Framing error Parity error Overrun error Data ready Status2 byte modem status Meaning Bit D7 D6 D5 D4 D3 D2 D1 DO Received line signal detect 1 Ring indicator Data set ready Clea...

Page 113: ...000102 Error status from the FD controller Type of Error Error Message Description TIME OUT Diagnostic processing not completed in time FDC FAILED Abnormal end for FD controller CRC CRC error detected at ID section or Data section DMA BOUNDARY OVER DMA transfer over 64KB DMA OVERRUN DMA transfer broken off halfway through RECORD NOT FOUND Designated track or sector not detected WRITE PROTECT Flopp...

Page 114: ... Read Command 3 Error Status The error status from the FD controller consists of seven parts as shown in the following example STO STI ST2 T H S N STO Status byte 0 ST1 Status byte l ST2 Status byte 2 T Track number H Head address S Sector address N Record sector length Codes for the status bytes are shown in the next page IT 99 ...

Page 115: ...Ol 1 IDAM isn t ID Detected Od t C doesn t corre spond not same Ol 1 1 as FFH C doesn t corre spond same as Ol 1 1 FFH H doesn t 01 1 correspond Rd oesn t 01 1 correspond Nd t oesn 01 1 correspond CRC d Pt oesn 01 1 correspond DAM isn t DATA detected Ol 1 1 DDAM is detected 0 0 1 CRC doesn t 01 1 1 correspond Overrun Ol 1 Doesn t end at last 01 1 sector IT 100 ...

Page 116: ...ot ready Ol 1 IDAM isn t ID Detected Ol 1 C doesn t corre spond not same Ol 1 1 as FFH C doesn t corre spond same as Ol 1 1 FFH Hd oesn t 01 1 correspond R doesn t 01 1 correspond t N doesn t 01 1 correspond CRC doesn t 01 1 correspond DATA Fault Ol 1 Overrun O01 1 D oesn t end at last ol 1 sector Write protected Ol 1 I 101 ...

Page 117: ...eted BAD CONTROLLER Controller may be damaged ECC ECC Error detected at ID section or Data section unable correction BAD ECC ECC Error detected at Data section but corrected BAD TRACK Designated track was formated with bad track flag DMA BOUNDARY OVER DMA transfer over 64K bytes INITIALIZE FAILED Abnormal end of controller RESET FAILED Reset processing was failed RECORD NOT FOUND Designated sector...

Page 118: ...ller 14 In read command 82 In write command 83 In seek command 8C In compare command at controller s ram area Cl In compare command at main ram area C2 9 5 10 Exit CRT Displays or step Test Procedures Printer Print Outs Type Insert DOS diskette in DOS must then be reloaded into DIAGNOSTIC drive A and strike any before it can be used again MENU key when ready This operation is equivalent to resetti...

Page 119: ......

Page 120: ...hnical Guide General ll Logic Unit ll Plasma Display Unit IV Keyboard Vo Power Supply Unit VI Floppy Disk Drive Vil Option Panasonic Portable Computer JB 3300 Matsushita Electric Trading Co Ltd P O Box 288 Central Osaka Japan ...

Page 121: ......

Page 122: ...roprocessor Unit o RAM Random Access Memory 1 Standard capacity 256K bytes 2 IC socket capacity 256K bytes Total Max 512K bytes o ROM Read Only Memory 16K bytes o Keyboard Interface O Interval Timer Speaker Interface o System Switch DIP Switch o PDP Controller I O Board PC board marking PLSY o FDD Controller o Parallel Port Printer o Serial Port RS 232C Current Loop o Option Slots 2 slots o Slot f...

Page 123: ...Interval Timer Speaker Interface The CPU board contains a programmable counter circuit which allows programming of an interval for the interval timer interrupt and a beep frequency The speaker is installed inside the system unit System Switch DIP Switch The CPU board has a 4 circuit DIP switch which establishes circuit operating conditions and program branch conditions PDP Controller The computer ...

Page 124: ...talled to this connector Serial Port The serial port in the I O board is used for communication with external device The serial port employs an INS8250 control LSI UART and is capable of communicating with an external device through either the RS 232C or current loop interface Option Slots The I O board has two option slots Both are IBM PC compatible 13 option board for either an IBM PC or IBM XT ...

Page 125: ...h Keyboard Figure 2 1 The system unit consists of a logic unit two FDDs or one FDD and one HDD power supply unit fan and a speaker The CPU board is installed parallel to the bottom of the unit The I O board and the FDDs are installing over the CPU board the I 0 board to the left and the FDD to the right Ii 4 ...

Page 126: ...LS373 uPD765 MAS MAO INTR Memory Expansion Flexible Buffer Memory Disk j oT VD7 VDO 5 25 ind ller FDDs DEN CS 1s5670 8237A 5 OMA XCS XXIOR XXIOW XRAS XCAS XWE Page Co 6245 LSi74 DMA Processor 5 troller CRT VIDEO rroke XAENOMA Generator Disploy Register Printer CRT ROM Address MPX cs CPU Address OT Decode L 240 Wie fus Buffer cs Decode L 244 Data ALE DEN Status Buffer System LS 243 Switch BIOR Buff...

Page 127: ...system Memory can be increased further to 640K bytes with an optional 128K RAM board for PC or XT inserted into the option slot The 32K bytes video RAM is the display memory Character codes and graphic patterns in the video RAM are read out with PDP scanning timing and displayed on the plasma display A 16K bytes ROM equivalent to the Intel 27128 is standard in the CPU board This ROM stores both a ...

Page 128: ...0 LZ a ZZ Video RAM e Video B8000 OZ ZZ 32K Bytes A0000 VA __e WA Optional RAM 128K Bytes Optional 80000 RAM Lcae 384K Bytes RAM Expansion 256K Bytes 60000 p 40000 jJ _ _ 1 RAM RAM 20000 256K Bytes 256K Bytes QO000 Z256K Byte System 512K Byte System Figure 4 1 System Memory Map II 8 ...

Page 129: ...tion The video RAM usage varies with the display mode Display modes are listed in Table 4 1 Table 4 1 Display Modes No of Display Memory Pages Display Character Box Display Mode Attribute TEXT 40 x 25 8 Blink 8 x 16 Non display Normal 80 x 25 4 Reverse 8 x 16 Intensity 4 dots pixel GRA 320 x 200 1 8 x 8 PHICS 4 gradations 640 x 200 1 2 dots pixel 8 x 8 640 x 400 1 1 dot pixel 8x 8 The video RAM is...

Page 130: ... H 16K Bytes Buffer Input Data Y ytes er Memory Y Even Buff Address honk MPX rnnncan Parameter CRIC Data Latch Data Latch Converter Even odd HD68A45S HD68B45S 7 Attribute Decoder Display Mode Video DATA 0 3 osest Generator Character Video Data a 4 Generator 1 8K Bytes ly MPX Status ytes a 4 Register Read Writ Timing Synchronous HS Cont 1 Generator Sugnal vs onctro er Generator SCK m 18 432 MHz Fig...

Page 131: ...ed into l digit 4 bit units and are input to the video generator which outputs these display dots as video signals to the PDP after adding gualifications such as attributes and color designation The MPU writes in or reads from the video RAM by refreshing the display while the video RAM is not accessed i e is idling The PDP controller outputs a WAIT signal to hold the MPU static while the video RAM...

Page 132: ... 4000 4 S _ od r rc 3 4 Page 7 g Page 3 0 Page 6 g 3000 Odd Odd Even Page 5 w D a Page 2 o o a oO Page 4 Ay Ay Ay 2000 a4 4 4 4 4 5 oC a Page 3 3 3 3 m vi Page 1 a u Page 2 1000 Even Even Even Page 1 Page 0O Page 0 0 40 x 25 80 x 25 320 x 200 640 x 200 640 x 400 Test Mode Test Mode Graphics Mode Graphics Mode Graphics Mode Figure 4 3 Video RAM Configuration ...

Page 133: ...acter D L Attribute D 6 Character D Attribute C 4 Character C 3 Attribute B 2 Character B Attribute A 16 Character A yr T T i ABC Dd i 40 or 80 columns 25 lines y PDP Screen Figure 4 4 Video RAM Configuration in Text Mode Figure 4 5 shows an attribute code in the text mode D7 6 5 4 3 1 DO Attribute Code aT7 aT6 aTS aT4 aT3 aT2 ari aro AT7 Blinking AT6 B Red oy 7 Y AT5 B Green AT4 B Blue AT3 F Inte...

Page 134: ...T7 Blinking AT6 Background Normal AT5 Background R Reverse AT4 Background Non display or turned off AT3 Foreground U Normal with underline when AT2 Foreground change the J11 short pin AT1 Foreground setting ATO Foreground F Full dots of character box illuminated Figure 4 5 Attribute Codes in Text Mode Il 14 Red color Green color Blue color Intensity Red color Green color Blue color ...

Page 135: ...P screen and display dot color designation is expressed by the brightness of light and shade on the PDP screen Offset Addr Offset Addr 076 543 2 100 O 1 2000 2001 50 51 2050 2051 2001 03 pd 2 pd1 do a ao atl t T 2000 07 D06 0 5 04 20A0 20A1 FO Fl 20FO 20F1 1fp 3 o2 d1t Do EVEN Oj 07 D6 05 0 4 t C co 2 Bits Pixel 4 Dots Pixel 0 0 Display Data C O 0 Y 7 PDP Screen oe a 2 _ V i Z Zz Figure 4 6 Video ...

Page 136: ... display mode One display dot one pixel is shown as two dots on the PDP screen in this mode Offset Addr Offset Addr D7 6 5 4 3 2 DO Same Pattern 2000 2000 fo7je 5 4 3 2 s oop SP 50 2050 AO 0 fo7 6 s 4 3 2 1 oof Ye 20A0 FO 20FO Figure 4 7 Video RAM Configuration in 640x200 Graphics Mode II 16 ...

Page 137: ...that all 32K bytes contained in this video RAM become a visual page Offset Addr QO Offset 4000 Addr 2000 _ _ _ 6000 50 4050 2050 6050 AO 40A0 20A0 60A0 4000 07 6 1s 4 3 2 1 Do opo FO 40FO 20F0 60F0 00D 6000 o7 6 5 BE 2 oo 2000 o7 6 5 GE 2 i oo EVEN 0 p7 6 5 4 3 2 Joo EVEN Figure 4 8 Video RAM Configuration in 640x400 Graphics Mode II 17 ...

Page 138: ...cipal functions of the logic unit are CPU board Accessing 16K bytes BIOS program ROM Control of standard 256K bytes maximum 512K bytes RAM Direct memory access DMA between memory and I O Interrupt control of eight interrupt levels OOVAO Peripheral I O interface PDP controller Keyboard interface Interval timer Speaker interface DIP switch O00 0 I O board 6 Peripheral I O interface FDD controller Pa...

Page 139: ...ge of the 5 V power is integrated by register R9Y and capacitor C17 Its level is detected by the 8284A circuit and is output as a reset signal The duration of the reset signal at this time is approximately 400 ms to 1 3 sec 5V od 8B284A RES 10 RESET RESET Lo xreser 5V 7 7 __ 4s RES Input a Detection Level 1 05 to 2 6 V RESET _ 400 ms to 1 3s Figure 5 1 System Resetting Circuit and Operation II 19 ...

Page 140: ...The leading and falling edge voltages of the 5 V voltage are detected by 4 2 0 2 V Vec 4 3 RY C2 yt O 1y RES X POR X3E X4F xX7C Q N 2 PSTS 8A 5V rt 4 2v 0 2v a 4d N X POR Figure 5 2 Anti Malfunction Reset Circuit and Operation The POR signal is used only with the WRITE GATE disable circuit inside the FD controller and the chip select circuit of the real time clock chip II 20 ...

Page 141: ...31818 MHz o 1 3 demultiplication 8284A 4 77 MHz CLK microprocessor clock o 1 6 demultiplication 8284A 2 3814 MHz PCLK I O control clock o 1 12 demultiplication 1 1932 MHz SCLK Timer clock A 4 77 MHz clock DCLK with a duty cycle of approximately 50 is produced from the microprocessor clock CLK using a delay device LS31 for DMAC o 1 3 demultiplication 50 duty cycle 4 77 MHz DCLK DMAC clock 5V 4 cuKE...

Page 142: ...em uses the 8288 as the MPU bus controller The MPU bus controller refers to the control status signals S2 to SO output by the MPU and produces the following control signals o ALE Address latch enable signal ALE Oo DEN Data enable signal DEN o DT R Data transfer direction control Signal DT R o MEMW Memory write signal AMWC o MWTC Memory write timing signal MWTC Oo MEMR Memory read signal MRDC o ITO...

Page 143: ... and Data Buses Of address bus lines ABO to AB19 ABO to AB7 eight bits and AB1i3 to AB19 seven bits are fetched and output by the address latch enable Signal ALE which is output by the MPU bus controller Bits AB8 to AB12 are output via the bus amplifier AB13 to AB15 need not be latched in this circuit however they pass through an address latch circuit In DMA operation the level of the AENCPU signa...

Page 144: ...YA Y Output only Data Bus DO7 to DOO Figure 5 5 Block Diagram of Data Buses The lower eight bits of the address bus are also connected via a bus buffer for the sake of fan out creating XAB7 XABO Wait state generation circuit The wait state generation circuit has two functions it generates wait cycles for the MPU and it adjusts timing of the command signals MEMR MEMW IOR and IOW which are output fr...

Page 145: ...and the levels of the ALE signal ENDDMA signal immediately after a DMA cycle as well as those of the PADVNC and ADVNC Signals go LOW one by one at each MPU clock pulse and command Signals are controlled by the input to the GBA pin of the bi directional buffer LS243 The command signals XMEMR XMEMW XIOW and XIOR are output by the trailing edge of the T2 clock cycle When memory or I O access is slowe...

Page 146: ...clock cycle ADVNC 2 When the MPU has accessed video RAM it waits several clock cycles until the video RAM becomes idle CRTWAIT 3 When DMA is in progress the MPU waits until DMA ends DMAWAIT 4 When the internal bus connector makes a wait request the MPU waits until the WAIT request is processed IOCHRDY All these WAIT requests are input to the 8284A circuit and the 8284A asks the MPU for a wait stat...

Page 147: ...MA WAIT 3d KENT S74 DCLK CK Oo MPU LSI74 D Q CLK CK Figure 5 8 Wait State Generation Circuit Wait state T4 TI tT2 T3 TW T4 ADVNC MIN 350sec RDY1 8284A Input L i coo eo 8284A Output NI LA MPU 8284A Wait Ready Detection Request Detection Point Point Figure 5 9 Wait State Generation Timing Chart II 27 ...

Page 148: ... other optional device The operation is outlined below 8087 NMI Enable Block 1 2 4D NPINSTL 8088 NM 1 X50 NPNMI De ee ee ee ee ee ee ee ee ee ee X7D DO7 x10G XWTNMI ly RESET _ _ise _ _ X100 XRESET S35 4 a 5V r HI 10 5 2 38 XENBIOCH Hfs LSO4 4 Vee ee ee Parity Enable Block Figure 5 10 NMI Generation Circuit 1 NMI register NMIs are enabled with this register I O address OOAO HEX Command To enable S8...

Page 149: ...ice in an expansion unit or other optional device becomes faulty the IOCHCK line becomes active and an NMI is generated This operation is enabled as follows I O address 0061 HEX Command To enable set bit 5 to 0 To disable set bit 5 to 1 II 29 ...

Page 150: ...the PDP controller All these memory devices are in the CPU board Figure 5 11 is the relationship between the memory devices and the memory map Address Hex FFFFF 16 FCO00 ROM K bytes EOOOO L COO00 B8000 Video RAM 32K Bytes 80000 Expansion 256K Bytes 60000 R aM 7 pa _ J 7 40000 EJF QO aa sa SO959 IC Socket 256K Bytes RAM 20000 00000 Figure 5 11 Relationship Between Memory Devices and Memory Map IT 3...

Page 151: ...utput signal DACKO from the DMAC determines whether or not RAM refresh is taking place LSOO ABI4 LS32 ABIS5 XROMSEL To ROM chip select To PDP controller XVRAMSEL XDACKO RAMSEL XRAMASEL A SEL To CAS decoding SEL B circuit Figure 5 12 Memory Address Decoding Circuit Short plug J13 has the following meanings o Short Without an expansion 256K byte RAM 256K byte system Oo Open With an expansion 256K by...

Page 152: ...L HIGH RAMASEL LOW SELA ceee LOW SELB LOW Standard 256K bytes selection O x x x x x yr RAMASEL HIGH Other output signals are the same as above Refresh operation selection 1 x x x x Short x No selection output 1 x x x x Open my RAMSEL HIGH RAMASEL LOW SELA 2 2 00 HIGH SELB LOW Expansion 256K bytes selection 0 1 1 1 x x x VRAMSEL LOW Video RAM selection 1 1 1 1 1 x X ROMSEL LOW ROM selection Xs Do n...

Page 153: ... Figure 5 14 shows a functional block diagram of a RAM access operation MPU addresses are converted into row and column addresses by the address multiplex circuit and are input to the RAM synchronized with the RAS and CAS timing Signals In normal RAM access by the MPU and DMAC input and output data is set in data bus lines DB7 to DBO after RAS and CAS are input RAM is refreshed every 16 us through...

Page 154: ...o a column address 4 CASO or CAS1 is selected and input to the RAM with the address decoder output via the delay device LS31 from RADMPX SOO XMEMR RAS LS 31 LS 31 Genera _ p MN CAS XMEMW tion Circuit RASO 5138 RAS1 SEL A SEL B Genera tion CAS RAMASEL Circuit CAS1 MWTC Timing AEN Genera 1 tion RAS DMARDY e Circuit RASO A AB17 to AB8 ccxess Bus Address RAM RAM XAB7 to XABO _ Multi 7 plexer 256K Byte...

Page 155: ...CLK RAMASEL XMEMW RAS RADMPX CAS MWTC CAS T4 TI T2 T3 T4 AT O el oe 3 Z Le Delay _ P Figure 5 15 RAM Operation Timing Chart II 35 ...

Page 156: ... 5 16 DMA Circuit Block Diagram The DMAC 8237A 5 has a 16 bit address and the DMA page registers produce the upper four bits AB19 to AB16 There are three DMA page registers one shared by Channels O and 1 and one each for Channels 2 and 3 The MPU I O command is used to write data to the DMA page registers The data is read from the DMAC in accordance with the DACK command DACKO to DACK3 and output t...

Page 157: ...EMR MEMW IOR and IOW command signals are inhibited When the MPU attempts to use the bus during a DMA cycle the DMAWAIT Signal is sent to set up a wait state until the DMA cycle is finished The DMAC sends a DMA address when the HLDA signal is returned The upper eight bits of the DMA are sent to the data bus and latched by the address strobe signal ADSTB DACK is sent to the I O that issued the DMA r...

Page 158: ...o DBO ADSTB DMAWAIT DACK XMEMR XIOR DMARDY ENDDMA rif te 3 tw SI SI SO So xo Nw Oo CS a WA A MPU no t in ve MPU in operation WP ly ih I NLA Se t Lo cs a MPU address DMA address DMA transfer data x 1 MPU data AI5 A Lo NO 7 8 tL XMEMW XIOW Figure 5 17 DMA Operation Timing Chart ...

Page 159: ...S 3P XEXPOCS 2 9F x68 ABB XFDCCS 3 3D X68 ABS XFDOCS 3 3D XRSCCS 3 3E K6A XBS2 XIOE XAENCPU X7E XAB5 X7E XABE6 X7E XAB7 XDMACS X5F XINTCS XIF XTIMCS 2 IE XPPICS 2 18 XDMAPGST X3G XWTNM X10 xXxlow X5G XCALOCS 3 3E XINIO 4 1H Figure 5 18 I 0 Address Decoder Circuit o During DMP operation AENCPU goes HIGH and I O address decoding is inhibited o During CPU operation decoding is enabled or disabled as ...

Page 160: ...oder IC LS138 outputs a SELECT signal to each I O using the 24S10 output and part of the address bus OFFF 7 O3FF L aan 7A rioppy Disk Color Graphics Ti Plasma Display Parallel Port 0378 O2FF O2F8 027F LLLLLLLZ_ Qoeremnscnesd Hard Disk Asynchronous Communications Parallel Port ns LLL MAC 8237 5 PIC 8259A Basic I O 4 TIMER 8253 5 PPI 8255A 5 DMA Page Register NMI Mask Register 0000 Switchable Figure...

Page 161: ... 7 7 7 7 2 7 7 7 7 7 7 7 7 7 7 7 7 7 3 4 5 6 7 8 3 9 O A B 6 Cc D 0 E F 1 1 2 5 6 Note All blanks are F HEX values on Address the address bus Bus 9 7 6 3 4 3 2 HEX differ from the D ROM data HEX Bits 1 1 212 21 21é40é id21 3F values in the 24510 ROM A7 A6 AS A4lA3 A2 Al AO FD previous table Input terminal 24S10 ROM 0 0 01 05 Output terminal 0 1 0 0 4 II 41 ...

Page 162: ...BASE F LOWER L UPPER 0007 CURRENT WORDCOUNT 1 4 CURRENTWORDCOUNT 4 YY READ DMAC REQUEST REACHED TC SET DMAC DACK DREQ FU PR TIM Er CHO yf 000 8 STATUS lee aye ys 1 O H 31H 21 1180 COMMAND IL iH 7 yf Ady Me SET REQUEST FONT CARE SELECT 0009 RE G fa jit tf td J Jf jf ft ft SET SINGLE MASK DONTCARE SK etvect OO OA Lp py pp yy yg REGISTER BIT gy pp SET MODE MOOE OOTYPE SELECT oo 08 Lapp tp tl REG TP e...

Page 163: ...ES a SET Kk pp ptt NMi REG EN t i a PARALLEL Hard disk PORT Lp pt pa a ee 0378 READ PRINT Data SET PRINT Data 0278 DATA 7 DATA Meee dt 0379 READ 1 0 PR 4 0279 STATUS lack jpst PE SLJER X X X ee ee O37A READ PRINT SEL SET PRINT INT SEL 44 027A STROBE xp xXpx PNTiin pnitjaP st STROBE xX X X JENPIN jAFYST CRTC SET CRTC INDEX O50 6845 fp peyy yy INDEX REG XixXsXp py yy READ CRTC Data SET CRTC Data cr ...

Page 164: ... ep pe yt yy 0 0 010 PINTPHTENTHHT O3F9 Most Signification Byte DLAB 1 1 a O2F9 ee es a OD O3FA READ INTERRUPT INT FUNC O2FA IDENTIFICATION 9 0 0 0 0 1 fi ty ty SET LINE Word OSFB y DL BR ST ODDPAR ST Length O2FB ioet opopoop CONTROL REG AB CNIPRIJEINJITY B O3FC SET MODEM OUTPUT O2FC yoyo bop pp CONTROL REG 0 0 0 12 1 jJRTSI STR O3FD READ LINE Rx Tx Br Fr Par OV Data 4 O2FD STATUS oO JEMPEMP IND E...

Page 165: ...as follows When an I O requests an interrupt a request signal enters the IR input The 8259A checks the mask condition and priority and sends an interrupt request INTR signal to the CPU The CPU outputs status SO L Sl L and S2 L to the bus controller 8288 in response to the interrupt request The the The The the The 8288 confirms that SO to 2 are all Ls and outputs INTA to 8259A in response 8259A sto...

Page 166: ... The display circuit controls the plasma display unit Figure 5 22 shows a block diagram of the display circuit follows a Interface with the CPU 1 2 3 4 5 6 7 Data bus transceiver VRAM data latch Display mode register Status gate CRTC parameter converter Memory address decoder WAIT circuit a Wait during VRAM access b Wait during I O write TI 46 The blocks are described as ...

Page 167: ...iplexer b CRTC address selector c Refreshing address counter VRAM data transceiver data latch a VRAM b VRAM access by the CRTC CHG and font data latch Graphic data latch Attribute decoder Video data controller a First converter b Second converter c Third converter CRTC control signal converter a DISPTMG cursor circuit b HSYNC circuit c VSYNC circuit Blink timing circuit Plasma output driver Plasma...

Page 168: ...ceiver CC Latch 1st Video Decoder Latch Status Resistor Bus Buffer CC Latch 2nd Parameter ROM AT Latch 1st ATO 7 CRTC Attribute Resistor No Latch Refresh Bus Decoder Counter Buffer Mode Resistor RFAO 7 DOO to AT Latch 2 nd DO7 Timing Generator Control NSYNC VSYNC DISPE CURSOR Modulater Blink Timing Figure 5 22 PDPC Block Diagram ...

Page 169: ...iver Circuit The data bus transceiver functions only in the following three cases 1 When the main memory is accessed 2 When data is written in VRAM 3 When the CPU reads the CRTC register The direction of data flow through the data bus transceiver is determined as follows Memory access by CPU From VD bus to DB bus T O read by CPU From VD bus to DB bus Any other time From DB bus to VD bus II 49 ...

Page 170: ...the DB data bus until the CPU or DMAC finishes the read Figure 5 24 shows the data latch timing eee MEMR CPU CAS VDO to 7 Valid 7 ore DBO to 7 old Data X Valid Figure 5 24 Data Latch Timing Chart Display Mode Register The 6 bit Display Mode register sets the display mode of the plasma display panel The Display Mode register is cleared by the RESET signal when power is turned on The display mode is...

Page 171: ...ws 1 2 3 4 5 6 HIGH TEXT HIGH in the TEXT 80x25 and GRAPHIC 640x400 modes GRAPHIC HIGH in the GRAPHIC mode CMDSET Stays HIGH after the WRITE instruction is executed to write into the Display Mode register 1i e after power has been turned on EN VIDEO Enables or disables the screen display HIGH when display is enabled HIGH GRAPH HIGH in the GRAPHIC 640x200 and 640x400 modes EN BLINK Enables blinking...

Page 172: ... DB1 DB2 yal wey DB3 ____ SYNC CRTD CS x XIOR c AEN Figure 5 26 Status Gate Circuit The status gate is enabled when it is read by the CPU The states of the status register is as follows DBO HSYNC DB1 Always LOW DB2 Always HIGH DB3 VSYNC HS YNC NN nN J VSYNC TO _ Se Figure 5 27 Status Gate Timing Chart II 52 ...

Page 173: ...CRTC Parameter Converter Circuit When written into the CRTC address register XABO LOW the data is converted according to ROM address input XABO CRTC Address Number Latch and DOO to DO7 values and output to VDO to VD7 The converted data is latched on the CRTC address register at the rising edge of WRTE write timing signal which is in synchronization with the CRTC clock pulse At the same time the da...

Page 174: ...ue is output to VDO to VD7 The data is then written into the control register at the trailing edge of the CRTC E signal In this case the CRTC address is not latched When the CRTC register is read data is output from the CRTC to VDO to VD7 In this case the CRTC parameter converter is inoperative Figure 5 29 shows timing for writing to the CRTC register iy 4 ao LL e crTCc Address No n 1 X CRTC Addre...

Page 175: ...4F XMEMR 4 3G XVRAMSEL 1 6F XABO 2C XVRAMWR The 1 2 3 VRAM EVEN 6 10C VRAM ODD 6 0E WE EVEN 6 68 WE ODD 6 6E Figure 5 30 Memory Address Decoder Circuit memory address decoder outputs are VRAM EVEN LOW when an even numbered address of VRAM is accessed when XABO is LOW The bus transceiver of the even numbered addresses is enabled VRAM ODD LOW when an odd numbered address of VRAM is accessed when XAB...

Page 176: ...ess of VRAM XABO is HIGH Makes RAM Write Enabled Figure 5 31 oO VRAM read timing chart XABO JF VRAMSEL J MEMR VRAM EVEN f Tad Oo VRAM write timing chart XABO J VRAMSEL MEMW CLK1 CRTADR VRAM EVEN 1 WE EVEN Figure 5 31 Memory Address Decorder Timing Chart II 56 ...

Page 177: ...2 6 3F XCLK1 4 we 6 3C CRTADR 76 T 6C 3 RQ 5 XWRTE 1G LSOO 13a 3 2 CRTC E 1E I1 4H XXIOR Figure 5 32 WAIT Circuit 1 Wait during VRAM access a b c dq The WAIT circuit generates a RAM WAIT when VRAM is accessed for read write The WAIT circuit requests WAIT to the CPU or the DMAC by means of CRT WAIT The access timing for VRAM changes from CRTC accessing to CPU or DMAC accessing CPU CAS goes HIGH the...

Page 178: ...hronization with CRTC At the rising edge of WRTE WAIT INH goes HIGH c Then CRTC WAIT goes HIGH and the WAIT request ends The CPU also ends the I O write operation ad WAIT INH then goes LOW and the I O WAIT circuit is enabled o VRAM access timing chart VRAMSEL _ oe CPU CAS wre t i RAM WAIT CRT WAIT o I O write timing chart CRTC CS 7 mo WRTE WAIT INH a S IO WAIT CRT WAIT Figure 5 33 WAIT Circuit Tim...

Page 179: ...ncy and the SHIFT clock pulse from the oscillator frequency 18 432 MHz The generator also provides the RSCLK clock pulse one tenth of the oscillator frequency to the 8251 Figure 5 34 shows the basic timing generator circuit and Figure 5 35 shows the signal timing Osc 18 432MHz VV VVVYVY S175 D Q q D Q 11Q q D Q BSCLK Q D Q 0 CLK 1 100 XRESET J 3 BASIC CLK 7F 7 4E 7 7F Le LSSi iP CLK4 172 CLK 1 4H ...

Page 180: ...the CLOCK input of the CRTC clock pulses are 8 x BSCLK in the TEXT 80x25 display mode and 16 x BSCLK in the other display modes This circuit also generates the output enable signal EN EVEN for display latch data The CRTC clock control circuit is shown below TEXTS8O CRT CLEK S D Q D Qe _ EN EVEN CLK1 CK Qe4 Basic CLK jCK Q _ EN EVEN R CLR CRT CASO LL h Figure 5 36 CRTC CLOCK Control Circuit If 60 ...

Page 181: ...mory Access timing in the TEXT 80x25 display mode by CRT CASO Signal timing is shown below Basic CLK CLK1 A TEXT80x25 CRTC CLK CRT CASO EN EVEN The Other Mode CRTC CLK mrs 7 4 7 Figure 5 37 CRTC CLOCK Control Circuit Timing Chart II 61 ...

Page 182: ... 3G XCLK3 U4 12N itSOO 18 ofizm pS REFADR ci 13 I 10D XRESET Figure 5 38 VRAM Access Timing Circuit Output signals of the VRAM access timing circuit are a b Cc d CRT SYNC LOW when VRAM access by the CRTC begins Makes CATADR HIGH ADV CRT Sampling signal to detect the end of the CRT cycle Sampling starts at the rising edge of CLK3 The CRT cycle ends when ADV CRT goes LOW CRT ADR HIGH when the VRAM i...

Page 183: ...M is refreshed Enables refresh RFA address output to the VRAM address CLK1 CLK2 CLK3 jl LCMAO i CRTSYNC L me ADV CRT __ Jiser Z CRT ADR RAM WAIT Le CPU ADR Pai REF ADR VRAM Address Figure 5 39 VRAM Access Timing Chart II 63 ...

Page 184: ... it performs a read or early write Ina refresh cycle it performs a RAS only refresh Figure 5 40 shows the RAS CAS timing circuit 3G CLK4 3C ADV CRT 3F XCLK2 3F CLK2 7H EN EVEN 2G BASIC CLK 3F CLKI 30 XCPU ADR 3G XCLK3 3C CRT ADR 3F XCLKI 3G CLK3 7 1D0 100 7F EN EVEN XRAS 6B RAS 175 4 4 MUX 4A S175 3 4 cas CPU CAS 5 7C V1 XCPU CAS 5 6B XCAS 6B XCRT CASO 7C CRT CASO 4H XCRT CASI 7C Figure 5 40 RAS C...

Page 185: ...e CRT cycle and CPU cycle modes That is low address when MUX goes LOW and column address when MUX goes HIGH CPU CAS A CAS signal to be output when VRAM is accessed in the CPU cycle mode CRT CASO The first CAS output signal when VRAM is accessed in the CRT cycle mode CRT CASI The second CAS output signal when VRAM is accessed in the CRT cycle mode CAS A CAS input Signal to VRAM enabled at low Two C...

Page 186: ...K CLK2 CLK3 CLK4 EN EVEN ADV CRT CRT ADR CPU ADR RAS MUX CRT CASO CRT CAS1 CPU CAS CAS RAS CAS Timing Chart Figure 5 41 CRTC 1 CRTC usually controls the raster scan CRT display circuit however it controls the plasma display II 66 ...

Page 187: ...RTC address selector and refresh address counter Figure 5 42 shows block diagram CPU RAS Address XAB2 to 5 VRAM Address CPU CAS Address AB1O to 12 MUX CPU ADR XABG 7 CPU RAS Address AB8 9 AB13 14 XAB1 CPU CAS Address CMA1 to 4 CRT RAS Address CRT CAS Address CMA9 to i1 CRT ADR CRT RAS Add CMA5 to 8 ress CMAO 12 13 RAO 1 CLK3 TEXT80 GRAPHIC SUPER GRAPHIC Refresh Refresh Address Address Counter RESE...

Page 188: ...a Ma MA Ma Ma Ma MA MA MA MA MA Ma Ma R TEXT oO 1 21 31 41 5 6 7 8 9110 11 12 1413 T C 80x25 cg MA MA MA MA MA MA MA MA MA MA MA MA MA TEXT 1 2 3 4 5 6 7 1 8 9110 11 12 1 13 A 320x200 MA MA MA MA MA MA MA MA MA MA MA MA RA RA D GRAPHIC 0 1 2 3 41 51 6 7 1 8 9110 11 12 1 13 D R 640x200 mMa MaA MA MA MA MA MA MA MA MA MA MA RA RA E GRAPHIC Oo 1 2 3 4 5 6 7 8 9110 11 12 1 13 S s 640x400 MA MA MA MA M...

Page 189: ... selector changes the relationship between the CPU addresses and the CRTC addresses Figure 5 44 shows the CRTC address selector circuit LS1I53 5 50 CMAl2 5 50 CMA I3 S SE RAI 5 50 R AO Ico oO Ic 8G 1C2 Coiumn 4 Address Column 5 Address 5 5F GRAPHIC 5 5G XSUPER TT Oo I 5 6C XCMAO 4 Tey 5 5F XTEXT8O IND O 1 Column 6 Address 3G CLK3 A Bae eee nee cme mines ciety em me eee me a a a Figure 5 44 CRTC Ad...

Page 190: ...s Figure 5 45 shows a refresh address counter circuit LS393 RESET xX REFADR x CLKI1 Figure 5 45 Refresh Address Counter Circuit Figure 5 46 shows an operation timing chart cuxt l po EN EVEN CRT ADR RAM WAIT REF ADR LS 393 L 1 Input d RFA RFA n YX RFA n 1 x RFA n 2 Address Figure 5 46 Refresh Address Counter Timing Chart II 70 ...

Page 191: ...on The direction is controlled by the VRAM WR signal CRTC access to VRAM In accessing VRAM from CRTC an even address address n and an odd address address n 1 in VRAM are read Simultaneously and are latched to the first data latch at the rising edge of the CRT CAS1 signal In the CRTC cycle mode VRAM is read twice by page mode read hence the next even address n 2 address and odd address n 3 address ...

Page 192: ...orch Ip a o a Uli p 0 FeCHBO to 7 He J LIcas Yi clk o EN EVEN we YY Wi Poa G LS374 a ZY 2nd Dato ZY fotch LZ cLK OC EN EVEN Le Poos pocnaaa5naa pasa7 LS245 v RaM 1 oe SSN DS BEKO rice LNILN P CAS N N oIR oC VRAM ODD rt NIN N NEN case 1 v rRam N N Ist Data HI na N N latch ail ie 07 SN N 0 Q ATBO to 7 l N RAS CAS LN CLK OC GRAPHIC e Odd Address N LS 374 Memory Block N 2nd Dato _ SN latch BINS cLk O ...

Page 193: ...a Latch Na DATA n 2 DATA n 6 EN EVEN CHBO to 7 F ODATA In X DATA n 2 C vataint 4 XK DATA n 6 DATA DATA DATA VRAM 1 Data PATA n 3 n 5 n 7 I ist Data Latch DATA n 1 M DATA n 5 2nd Data Latch x t DATA n 3 C DATA n 7 EN EVEN ATBO to 7 X paTaint i X DATA n 3 X vata in 5 XK DATA n 7 Figure 5 48 Timing Waveforms TEXT 80x25 ...

Page 194: ...n 2 EN EVEN f CHBO to 7 COAT n x DATA tn eee DATA n 2 x DATA n 2 ATA DATA DATA D VRAM 1 Data PATA ay n 3 n 3 n 5 ist Data Latch x DATA n 1 4 DATA n 3 2nd Data Latch Xx DATA nti x EN EVEN ATBO to 7 X __iatainti d Xo patainei SR DATA int 3 Xs DATA n 3 1 ma ke aoi f e fc ATBO to 7 DATA n 1 DATA n 3 Sf Figure 5 49 Timing Waveform Not TEXT 80x25 ...

Page 195: ...5 50 CHG Font Data Latch Circuit The CHG character generator has two fonts Single font and bold font each consisting of characters in an 8 dot x 16 dot character Matrix The single font and boid font are switched by the foreground intensity bit AT3 of the attribute code The single font is selected by AT3 0 and the bold font by AT3 l Connecting jumper J6 to BO allows the bold font to be selected AT3...

Page 196: ...rising edge of CLKI1 and output to LCHGO to LCHG7 Figure 5 51 shows a graphic data mix data latch circuit diagram EVEN ODD Memory Oata Mix Buffer LS373 LS374 L CHG 7 L CHG 6 L CHG 5 L CHG 4 L CHG 3 L CHG 2 LCHG 1 L CHG 0 6 7H EN EVEN 5 5F XGRAPHIC ATB7 ATB6 ATBS ATB4 ATB3 ATB2 ATBI ATBO 6 10C 6 3F CLKI Figure 5 51 Graphic Data Mix Data Latch Circuit Figure 5 52 shows an operation timing chart II 7...

Page 197: ...y ist 2nd Data Latch Output rN _ fEven Odd Memory x Data Mix Buffer L sp DATA n 1 p DATA n 3 4 DATA n 2 Ez DATA n Output wefe ATBO to 7 ER ata 6 X oan 1 MR ata in 2 pX vata in 3 CLK1 N LCHGO to 7 Xv DATA n XK DATA n t KX pata tn 2 Figure 5 52 Graphic Data Mix Data Latch Timing Chart ...

Page 198: ...inking The decoded data are latched to LS174 at the rising edge of CRTC CLK EN BLINK Blinking Pulse Cursor PROM E TBP24S10 AT Q A6 AS Qi AG A3 Qe2 A2 Al A L REVERSE LINH L UNDER ATB7 ATB6 ATBS5 ATB4 ATB3 ATB2 ATBI ATBO 9 UNDER LINE XRTC CLK XGRAPHIC Figure 5 53 Attribute Decoder Circuit Underlined display can be enabled or disabled by short plug J1l It is disabled when shipped from the factory II ...

Page 199: ...ta to video data to be output to the plasma display The converted video data is latched to the video data latch at the rising edge of the SHIFT signal Figure 5 54 shows a video data control circuit diagram lst Converter 2nd Converter LS51 1 2 LS51 2 2 IG 3rd Converter Video Data Latch poo qq oT4 TBP24SI0N TBP24SI0N LS174 4 6 LCHG7 AO QO 6 Q 5 4 t 3 y 2 1 0 I GRAPHIC LINH LREVERSE CURSORDLY LUNDER ...

Page 200: ...t data x LCHG n Lower bit data XLCHGin 1 Upper bit data x o Other Display Modes Oo TF r L_ LCHG7 to 0 x LCHG n KX en Xv 5 reer 4 Bit Conver LCHG n Upper LCHG n Upper LCHGint Upper LCHG n l Lower LCHGin 2 Upper V LCHG nt 2 Lower sion Data bit data bit data bit data bit data bit data it data Figure 5 55 First Converter Timing Chart 2 Second converter The second converter enlarges each bit of 4 bit d...

Page 201: ...0 0 0 MD3 MD2 MD1 MDO MD3 MD2 MD1 MDO 1 0 0 1 MD 3 MD2 MD1 MDO MD 3 MD 2 MD1 MDO 1 0 1 1 MD3 MD2 MD1 MDO MD3 MD2 MD1 MDO 1 0 1 1 MD 3 MD2 MD1 MDO MD3 MD2 MD1 MDO ar tft fe e oes vme mos oo a 2le ale mol CanRASTER 1 1 0 1 MD3 MD2 MD1 MDO x Ds MD3 DO MD1 a tft o mms woo wos woo x fO3 FOS OO too Sonear 1 1 1 1 MD3 MD 2 MD1 MDO x bs MD3 DL MD1 j L_ For dot pattern control in the GRAPHIC 320 mode L____...

Page 202: ...1 1 1 1 F Cursor in non display 0 0 1 0 ND3 ND2 ND1 NDO 0 0 0 0 O Cursor in reverse Cursor in 0 0 1 1 ND3 ND2 ND1 NDO 1 1 1 1 F full dote 0 1 0 0 ND3 ND2 ND1 NDO ND3 ND2 ND1 NDO ND Normal 0 1 0 1 ND3 ND2 NDI NDO 0 0 0 0 O Non display 0 1 1 0 ND3 ND2 ND1 NDO ND3 ND2 ND1 NDO ND Reverse 0 1 1 1 ND3 ND2 ND1 NDO 1 1 1 1 F Full dots 1 0 0 0 ND3 ND2 ND1 NDO 1 1 1 1 F Under line in normal 1 0 0 1 ND3 ND2 ...

Page 203: ...and adjusts the display timing Each of these signals is described below 1 DISPTMG CURSOR circuit The DISPTMG CURSOR circuit synchronizes the DISPTMG and CURSOR Signals output from CRTC with video data Figure 5 56 shows the circuit diagram 5 5E DISPTMG 5 5E CURSOR x DISP TMG D2 x CURSOR D1 CURSOR D2 CLK 1 Figure 5 56 CRTC Control Signal Converter Circuit II 83 ...

Page 204: ...NC 6 3F XCLK iI HSYNC OLP I 10D XRESET HSYNC STA Figure 5 57 HSYNC Circuit 3 VSYNC circuit The VSYNC circuit receives the VSYNC signal from CRTC and generates from it a VSYNC DLY signal to be output to the plasma display Figure 5 58 shows VSYNC circuit diagram RAQ 5V 5V Lsti2 H_Lsos Tesii2 J Q i2u a VSYNC DLY I2J i2G VSYNC _ eK dot iD LSO8 2 2Gie A K 12H J15 a 2 S393 RA l uf Io tH m XV SYNC 8A 3F ...

Page 205: ...shows a blink timing circuit diagram LS20 L1H p XCHR BLINK 5y R45 KCURSOR DLY 560 oF bl CU 2 MH D2 fo 98 5V Ti3zp7c LN25RP ABCD VSINC Latch _ cK12H 13 Cc OD LSOO ayy L S393 GRAPHIC 5 SF Figure 5 59 Blink Timing Circuit Figure 5 60 shows an operation timing chart VSYNC Latch 10 205 LIS B UL 2Q 20 Cursor Blink 225 7 Character Blink _ 8 field time 8 field time Cursor OFF Cursor ON 16 field time _ i6 ...

Page 206: ...nce LSOO 7G XVSYNC XOATAO KDATAO XDATAI XDATAI XDATA2 XDATA2 XDATA3 XDATA3 i i DSS 310 27 xX 8 XSF TCLK XSFTCLK xvs XvS XHS XHS XPOP CLR XPDP CLR LL JjLs240 Figure 5 61 Plasma Driver Circuit DATAO to DATA3 output lines are enabled when both the EN VIDEO signal in the display mode register and the vertical sync signal VSYNC are HIGH The other control signal outputs are kept enabled II 86 ...

Page 207: ...OPEN PDP CLR Figure 5 62 Plasma Reset Circuit Plasma interface signals The five plasma interface signals are described as belows 1 DATAO to DATA3 4 bit parallel display data signal The dot lights when the Signal line is low 2 SFT CLK Data transfer shift clock to shift display data into the shift register 3 VS Vertical sync signal Moves scanning to the top display line 4 HS Horizontal sync signal G...

Page 208: ...nchronous RS 232C communications are available There are also two option slots for IBM PC compatible boards The RAM expansion option is also described This chapter also describes the proper settings for the internal configuration DIP switches for the computer The following diagram illustrates the positions of the external ports found on the lower left hand side of the computer Figure 5 63 II 88 ...

Page 209: ...on LSI75 PCLK 9 54MHz Clock generator LS i25 Software reset buffer LS t25 xR Data transfer buffer 1l I C P Overcurrent protective parts Figure 5 64 Keyboard Interface Block Diagram 1 Serial data creation When a key is pressed 2 byte data KBDATA is input to this circuit in synchronization with the clock pulses KBCLOCK When the key is released Key Off data is input The input data enters the serial p...

Page 210: ...sets the interrupt request block and the serial parallel conversion block sets KBDATA to the H level to keep it in the ENABLE state and prepares for the next data transfer When power is supplied the 8255 5 s output PB6 is set to the L level according to the programmed condition and KBCLOCK goes to L With this signal the keyboard performs self diagnosis When no key is pressed the keyboard outputs O...

Page 211: ...S KBCLOCK U u u uo ou Ui U u SC _e TRO Figure 5 65 Keyboard Timing bob Parallel interface circuit The printer interface a parallel interface connects a printer It conforms to Centronics specifications Figure 5 66 shows a block diagram of the parallel interface circuit II 91 ...

Page 212: ...O ESTB EAUTO FEED XT EINIT ES LCT IN EBUSY External ESLTC Control Control EACK Signal Signal EERROR Latch Gate RESET Drivers Control Signal Gate Status Gate PXIOR XIOW Printer IO Command Decoder PRTCS XAB1 XABO Int Enable Figure 5 66 Parallel Interface Block Diagram ...

Page 213: ... line is LOW EINIT This signal is normally at a high level When it goes to low level the printer is reset to its initial state and the printer buffer is cleared ESLCT IN When this Signal is at a low level the printer is possible to entry the data But this signal is fixed to low level by the printer EAUTOFD XT When this signal is at a low level paper is automatically fed one line at a time after pr...

Page 214: ...g cases 1 During data entry 2 During printing operation 3 In OFF LINE mode 4 During printer error states EPE This signal goes to a high level to indicate that the printer is at paper end The level of the EPE signal is HIGH when the ribbon ends EERROR This signal is normally at a high level and goes to a low level to indicate that the printer is in paper end off line and or error state The level of...

Page 215: ...READ PRINTER COMMAND PLBG2 O 2 7 A Note Either of the I O addresses 278H 27FH or 378H 37FH may be set by means of a short circuit plug J3 When the equipment is shipped the I O address is set to 378H 37FH 3 Data latch and data gate The data latch latches output data from the CPU to the printer The CPU can also read output data by enabling the data gate 4 Control signal latch and control signal gate...

Page 216: ... O address 37A HEX For an interrupt an interrupt request to the interrupt controller is generated by the EACK signal of the printer using IRQ7 Data output timing Figure 5 67 shows data output timing to the printer and printer response timing L LK 4 aN 4 J Print Data n SXPrint Data n j fo p Figure 5 67 Parallel Interface Timing Chart II 96 ...

Page 217: ...Hz is possible 8255 5 PBI m SPK DATA PBO mm SPK GATE So PC5 m SPK FRQ PC 4 m SPK OUT 5 _ S me IA 4Y Ww ron 5 8253 CLA CLA 75477 OUT 2 I O Board GATE 2 CPU Board er CLK 2s Le 1 19318 MHz Controlled by SPKDATA and SPKGATE output by 8255 5 and by SPKFRO output by 8253 SPKFRO and SPKOUT are input to 8255 5 Figure 5 68 Speaker Interface Block Diagram It 97 ...

Page 218: ...50 Connector for ACE RS 232C DB7 to DBO e EIA EDTR _ Level ERTS Driver ETXD XAB2 to XABO _ RSC CS XIOW XIOR XCDT Current e XCDR RSCLK Loop RCDT Circuit RCDR IRQ4 cu RESET ae 1 RS 232C tL f Current Loop Jumper ERXD EIA ECTS Level EDSR Receiver f EDCD ERI Figure 5 69 Serial Interface Block Diagram II 98 ...

Page 219: ...rent loop jumper The initial setting is the RS 232C interface 2 EIA level driver and receiver a Transmission receiving level converter circuit This circuit converts the TTL level signal to the voltage level specified in RS 232 V 24 5V 12V l2V Te T 8 5 ee 2 882 7 75150 Le B25 I1A tov Peripheral Device canon NC ie 2 cee eae 7 12 5 _ i 75154 Lee Figure 5 70 Voltage Interchange Circuit II 99 ...

Page 220: ...cuit Set Bit 3 of the MODEM control register to 1 to enable an interrupt request from 8250 Interrupt requests are produced to the interrupt controller by IRQ4 NOTE Either of the interrupt level IRQ3 or IRQ4 may be set by means of a short circuit plug J6 When the equipment is shipped the interrupt level is set to IRQ4 II 100 ...

Page 221: ...ERRUPT ENABLE 0 2 F 9 O03 F9 L H L L H O SET DIVISOR LATCH MSB 0 2 F 9 O3 FA L x L H L I READ INTERRUPT IDENTIFICATION 0 2 F A FB 0 3 L x L H H O SET LINE CONTROL REG 0 2 F B O3FC L x H L L O SET MODEM CONTROL REG 0 2 F C O3FD L x H L H I READ LINE STATUS 0 2 F D OSFE L x H H L I READ MODEM STATUS 0 2 F E Note Either of the I O addresses 2F8H 2FFH or 3F8H 3FFH may be set by means of a short circui...

Page 222: ... 6 Data format Figure 5 73 shows a typical asynchronous transfer format TxO Start 03 04 05 06 D7 Prity Stop 2 Mark Bit DO 01 D Bit Bit Figure 5 73 Asynchronous Transfer Format II 102 ...

Page 223: ...oller creates an interface timing between DMAC and FDC in DMA transfer Clock generator This generates a 16 MHz clock frequency and supplies it to the FDC and the VFO The frequency is first supplied to the VFO where it is frequency divided into a 4 MHz clock and supplied to the FDC VFO circuit This circuit separates data read from the floppy disk into data and clock and creates data and windows Ref...

Page 224: ...RST DRIVE SEL4 ed MOTOR ON Foc Buffer witC RST INDEX INDEX 21 X DACK RW SEEK Y Decoder oO WPRTT WRITE PROTECT TRK OO Buffer TRACKOO Buffer SIDE SIDE SEL INT DIR _ DIRECTION _IT4 STEP 07 La WRITE DATA DO WOA GATE XWR WE a WRITE GATE PSO XRD PSI BLOCK cs READ DATA 4m PRECOMPESATION AO CLK O1 WCLK E Buffer WINDOW ROATA ROAIAL a SYNC __ I MFM DRQ XG Voltage Detection VFO 16H Clock Generator Figure 5 7...

Page 225: ...IVE SEL2 KX3D XFDDCS X3C XXIOW K3C XRESET XDRIVE SEL TE gLle UPD765A L832 tS XMOTOR ON LSo4 Looe Buffer Figure 5 75 FDD Control Command Buffer Register Circuit MSB LSB DO7 6 5 4 3 2 1 DOO 4 4 DOO DO1 Drive No L__ DRIVE SELECT 0 0 1 0 1 2 FDC RESET 1 0 3 Low active 1 1 4 INTERRUPT DMA REQUEST ENABLE High active y MOTOR ENABLE x Do not care DO4 DO5 DOG DO76 Motor on The motor rotates when any 0 bit ...

Page 226: ...uest signal from the FDC more than 1 26 us and sends it to the DMAC for the following reason The minimum time for the DMA to return DACK after receiving a DMA request signal occurs when DREQ of a higher priority rank is generated after DREQ with a low priority rank is generated and is for two cycles of the DMAC clock 420 ns At least 1 6 us is required after the FDC generates DREQ and before readin...

Page 227: ...signals Figure 5 77 shows a timing chart The output signal WDA write data from the FDC synchronizes with the 4 MHz clock CLK in IC LS175 and is delayed by 250 us IC153 determines using PSO and PS1 which signal of LS175 should be selected The selected signal is resynchronized by LS175 and output to the FDD as a precompensated signal 250 PSO 1 GB Figure 5 77 Precompensation Timing Chart It 107 ...

Page 228: ...ounter timer consisting of three of 16 bit counters The uses of these counters are given below Table 5 10 Usage of the 8253 5 Counter Channels 8253 5 Channel Usage Mode CLK MHz 0 Internal timer 1 19318 1 Memory refresh 1 19318 2 Beep frequency generator 1 19318 In Modes 2 and 3 OUT H if GATE L Memories are refreshed every 4 msec Refer to the data sheet for more details on 8253 5 II 108 ...

Page 229: ...5 78 System Switch Circuit a Definition of plasma display select switch SW2 The plasma display select switch is located in the port compartment at the lower left hand side of the unit and can be operated from the outside oC0 Fy Oljo Position ON Plasma display ON OFF Plasma display OFF II 109 ...

Page 230: ... Position 1 2 3 ON OFF Position 1 8087 enable OFF disable ON default 2 seccce Reserved 3 cecee Reserved The system configuration is defined by the input data of PPI 8255A 5 PC Register as follows HEX Port Address 0062 PB3 Oo PB3 1 PCO wpe or 1 I Position 1 8087 ya or 2 Reserved position 2 O one drive 1 two drives 3 Reserved position 3 oO Figure 5 79 It 110 ...

Page 231: ...board and the DIP switch interface and port to the DIP switch interface respectively For more details refer to the data sheet d Short plug setting The short plugs on the CPU and I O boards are set as follows when the equipment is shipped On the CPU board J7 2 EP Short JB e EP Short Jil UNDE Short J13 with expansion memory Short without expansion memory Open On the I O board J2 aeee 232C Short J3 3...

Page 232: ...ded in the extension unit KEDGATE X4F EDOIR X4F KEDACK 2 X5E a e ame ae ae cee oem ee ee oe oe eam X2E EXRESET ee em ee Oo OQ tee ee us KINTIO X2F X2F XEXPDCS ASO EALE X50 X EMEMR X50 X EIOR KX7A X EXTMEM 2 1OF XEINTIO rc I L Figure 5 80 b Description of circuit 1 The 74LS74 11B 1 generates a select signal to switch the gate and DIR signals of the data bus This signal is input to the select signal...

Page 233: ...ls delayed 150 ns by the 74LS31 are output The 74LS31 5C generates a DIR signal delayed by 150 ns The 74LS31 6C generates a gate signal delayed by 150 ns The 74LS74 11B 2 generates a reset signal for the 74LS74 11B 1 The circuit in the dotted line square in Figure 5 80 generates the conditions of a gate and DIR signals The 74LS02 10C 1 changes the direction of the data bus from A to B for option m...

Page 234: ...ller IRQ2 IRQ7 Interrupt request lines 2 7 Signals on these lines are input from I O adapters to the inter rupt controller to indicate interrupt request to the processor IRQ2 has the highest priority while IRQ7 has the lowest While the rising leading edge of these signals causes an interrupt request they may be held high until an acknow ledge signal INTA is returned from the processor DREQ1 DREQ3 ...

Page 235: ...al While this line is low the addressed I O device places its data on the data bus This signal is issued from the processor or DMA controller TOW I O write line Active low I O write control Signal While this line is low the addressed I O device reads the data from the data bus This signal is issued from the processor or DMA controller RESET Reset Active high signal synchronized with a falling lead...

Page 236: ...etween the processor and the DMA controller TC Terminal count An active high pulse to indicate that the terminal count on the pertinent DMA channel has reached zero CLK Processor clock The basic clock furnished to the microprocessor It is created by dividing the master clock by three and it has an interval of 210 ns with a duty cycle of 33 The clock frequency is 4 77 MHz TOCHRDY T O channel ready ...

Page 237: ... RESERVED DB1 12 V DBO GND BiO A10 T O CH RDY MEMW AEN MEMR AB19 IOW AB18 IOR AB17 DACK3 AB16 DRQ3 ABL5 DACK1 AB14 DRQ 1 AB13 DACKO AB12 CLK B20 A20 AB11 ITRQ7 AB10 IRQ6 ABQ IRQS AB8 IRQ4 AB IRQ3 AB6 DACK2 AB5 TC AB4 ALE AB3 5 V AB2 OSC AB1 GND ABO Figure 5 81 Connector Pin Assignment II 117 ...

Page 238: ...sition 2 Reserved Position 3 Reserved Short Plugs J2 2 2 RS 232C current loop select RS 232C Current loop J3 Printer I O address select 378H J4 RS 232C I O address select 3F8H J5 eee FD version HD version JO wesc RS 232C interrupt select TRQ4 II 118 Short Short Short Short Open OFF ON OFF OFF Short Open Short Short Short Open Short on on on on shipment shipment shipment shipment ...

Page 239: ...6 Replacement Parts List and Drawing IT 119 ...

Page 240: ... C85 C87 to C94 C2 3 4 YJ104B102KF Ceramic Capacitor 4 15 50V 1000PF CN6 EMCS0250M Connector 1 CN7 EMCS0252M Connector 1 CN8 EMCS0352M Connector 1 oo Pcs Ref No Parts No Parts Name Description ot Remarks CN9 YJJJCO0710B4 Connector 16P 1 CN EMCS0451ML Connector 1 CN EMCS0651 ML Connector 1 CN YJ7664 62S Connector 64P 1 CN5 YJ5276 05A Connector 1 D1 MA162 Diode 1 D2 LN25RP LED 1 FILTER1 YJBNPOO2 02 ...

Page 241: ... 1 12J 11R SN74S10N IC 1 1D 7P M74LS125AP IC 2 6F 12P SN74S11N ic YJDILB40P8JC IC Socket 40P 1 Ap SN748138N ic 6E 12K M74LS02P IC 2 MN SN74S158N ic ie M74LSOOP IC 100 110 SN74S175N Ic 2 12F 12M 7A 5H 11M SN74S74N IC 3 oN M5L8284AP LSI 1 4E SN75477P IC 1 1J UPD8088D LSI 1 IR4 YJARBO0071B4 Resistor Array 1 8H M74LS139P IC 1 IR2 35 YJARB00201B4 Resistor Array 3 10D M74LS157P IC 1 IR1 YJARBO0501B4 Res...

Page 242: ...ON ROM 64k 1 8B 11C 12E M74LS174P Ic 4 CN YJJDKO2820B4 CN Cable 1 6G 2C M74LS164P IC 1 4M 3P M74LS138P IC 8J 8K 8L M74LS257 AP iC 8M 5F 11H M74LS20P iC 2 3C 1E 2M M74LS244P IC 3J M74LS243P IC 1 11D M74LS240P Ic 1 5N 5P M74LS158P IC 8C 6D 7F M74LS32P IC 4 6K 12L 10P 12H M74LS393P IC 2E 3E 10G M74LS373P IC 6 1K 71L 10N 9D 10H M74LS245P IC 4 10J 2K x1 YJJF X00360B4 Crystal Oscillator 1 x2 YJJFX00390B...

Page 243: ...6 1 CPU Board PLSMX oO wv Ox 4 oO W TI 123 ...

Page 244: ...D BOD 3 DO1 X3H CENCPU X3F 28f 3 BD o XDEN X5D 5V NDE ai DOO X3H X2D 2 4 IRQ _ iz heh at OT R X5D 5 1E X10C 6 Vee LS373 X2C XCLK 2 10C 1RQ2 20 iR2 5 aw ALE X 5D X8C 2 9E DMARDY 4READY 40 aB7h sf 2 XABT X8G 4 IF 6 38 8A XADVNC KIB X3F SV 5V IRS __ XRESET 2 10 1RO3 2Uip3 RIBTreepeeey X20 DCLK yCLK AG go ABO h IG 2 XAB6 X8G 4 IE 6 3B 8A X10D 2 10C 3 3E 1RQ4 22 1R4 ihrako 4 psig eee i tS243 sssss xX3A...

Page 245: ...2B 1 10D AEN I 10C DMARDY D 1 7F XABO MAO X5G 1 6B ABI4 7F XAB2 MAI X5G 1 68 ABS 7E XAB4 MA2 X5G 6B ABI I l 7E XABGE MA3 X5G 6B ABI3 E 1 7F XABI MA4 X5G 1 6B ABS 7E XAB3 MAS X5G 1 6B ABIO l 7E XAB5 MAG X5G 6B ABI2 a 7E XAB7 MAT X5G 6B ABI5 X4C RADMP X LS5I 2 2 1 6A ABI7 5G MAB X5G F 1 6A ABIG TS Ls0s 3 R44 22 4F XMEMW tr WW XWE X5G 5V Lo Lsi25 Poy R4l Ra3 Ra2 X4D X4E X4F 2pwus ss 47 8 440 XVRSEL 7...

Page 246: ... 4 3G CRTCCS cs RAO RAO 6 4D 7 IC 7 1G 6 3F XCLK1 2 5 LS139 1 6F XABO RS RAI 6 3C CRTADR Q 3 aq G YO p VRAM EVEN 6 10C _ 6 7H CRTC CLK CLK RA2 RA2 7 18 04 734 pio VRAM ODD 6 I0E b I 10D RESET RES RA3 7 18 13 12 3p 9 _ RAG 1 4F XMEMR 8H 1 4E DT R R W ey III DLSPTMG 01 SP TMG 7 IF 4 36 XVRAMSEL 4 10D CRTC E CUDISP CURSOR 7 IF YOp esta TSYNC HSYNC 7 IG 1 6F XABO 314 b WE EVEN 6 68 E VSYNC VSYNC 7 I1G...

Page 247: ...I 3 36 e 1g 102 qi 2 LS290 3G CLK4 R3 IOR 3C ADV CRT 4 22 3F XCLK2 WA 6 XRAS 6B 3F CLK2 _ 7H EN EVEN RAS S175 4 4 MUX 4A F Refresh Counter 2G BASIC CLK CLK1 4H 7F 7 1E CLK 1 7G IC 5 6D 7 1A 7 1G CLK2 IC 7E 3 oll 175 3 4 KE CLK2 7E 3F CLKI 4 124 of Oo cpu cas 5 7 CLK3 76 3D XCPU ADR _ Q10Q 7 BSCLK CLK3 1D 7G 4E LSo4 ot CLK4 7E sO T XCPU CAS 5 6B 13 CLK S10 Feoit 3G XCLK3 z 2 rq2 XCAS 6B 3C CRT ADR ...

Page 248: ...LKI i 10D XRESET 5 56 RAI 5 56 CMDSET 5V A z Pull up 5V T 5V 4 GND 7G XVSYNC i LS5t 2 72 LS51 i72 1G 47K x 4 LS174 4 6 2 TBP24S10N TBP24S10N D AO XDATAO 5 Al D A2 Qi XDATAI D A3 A4 Q XDATA2 D AS5IIE D AG Q XDATA3 3 AT 13714 DSS 310 271 x 8 XSFTCLK Xvs XHS XPDP CLR _ _ J s24o 5V C69 TBP24S 0N 1Op I6V A7 Q oa 8 GND A6 9 j A5 Qi 10 12 15 CNS3 HiIFSFA I16PA A4 A3 Q AZI0E Al Q 6 4H SHIFT 6 2G BASIC CLK...

Page 249: ...AB 1 6C AB I 6C AB I 6C AB 1 6B AB 1 68 AB On On OO fF WN 2 3 4 5 6 7 8 9 1 68 ABIO 1 6B ABI 1 68 ABl2 1 6B ABI3 1 6B ABI4 I 6B ABIS 1 64 ABI6 1 6A ABI7 1 6A ABI8 1 6A ABI 1 4F KIOR 1 4F X1OW 1 4F XMEMR l1 4F XMEMW 1 3A CLK 4 4H XINTIO 1 7G TC 1 100 AEN 1 7F XAB DREQO 1 7F 1 7F XABO 1 10G X TIMCS 1 5G KX IOR 1 5G XX1OW SPKOUT 4C SPKFRQ X4B SPK 3 3F SPKGATE X4B SCLK x6C 7F XDACKO SPKDATA X4B 1 3A R...

Page 250: ...5 5276 05A 1 6D DB 4 DB3 DB2 12V DBI DBO GND XAB3 ne EMC SO252M XAB2 1 7E Xx AB XABO 1 4H XIOW 1 4H XIOR 1 3A RESET 1 10D RESET 1 7F DREQ2 1 7F DACK2 1 IOF XFDDCS I 10F FDCCS 1 10G RSCCS 1 10F XPRTCS 1 1I0H CALDCS 1 38 PCLK 6 2E RSCLK 1 76 TC l 1B IRQ4 l 1F IRQ6 1 IF IRQ 1 1B POR 2 5F SPK GND 5V 2 2D SECOND DRIVE CN 2 JDKO2820B4 yl 3 4 6 7 10 If 137 ...

Page 251: ...pacitor 1 50V 470PF CN11 CN26 EMCS0451 ML Connector 2 CN14 YJJJCO0640B4 Connector CN15 YJJJCOO650B4 Connector 1 CN19 YJ5275 05A Connector 1 Ref No Parts No Parts Name Description Remarks CN20 YJ7634 62S Connector 1 CN12 YJ7650 62S Connector 1 CN21 YJ8564 45C Connector 1 D6 D7 D5 MA162 Diode 3 L6 YJBNPOO2 02 Filter 1 13G YJJQL00181B4 VFO LSI 1 13E PST518A Reset IC 1 5C 6C SN74LS31 N ic 2 5E SN74LS3...

Page 252: ... 1 4W 5 6kQ i 8 11G SN74LS273N iC R29 ERD25TJ682 Carbon Resistor 1 ALS367A Ic 1 4W 6 8kQ aF SN74L N 1 R1 ERO25CKF49R9 Metal Oxide Resistor 1 SF 11C SN7406N IC 2 1 4W 49 92 7D SN7407N IC 1 SW2 YJAS1D 6M Switch 1 12D 12E SN7438N IC 3 DSW1 YJDTS 3H Dip Switch 1 7F INS8250N B iC 1 SYNC YJTM 027 Check Pin 6 1G YJPS 2006B Photo coupler 1 CNTL CN22to YJAJCO2910B4 Connector 3 WINDOW CN24 RDDATA GND INDEX ...

Page 253: ...6 2 T O Board PLSY PLS Y 5150 75150 RDDATA SED9420CAC Figure 6 2 PLSY Parts Location It 141 ...

Page 254: ...CWRITE DATA reset O44 RESET 2 7A xrReset O82 XRESET X4B 2 2 1A XSTEP prea2 OFF DREQ2 x4D 20 xpacke O48 XDACK2 xX4C N C 2 4 34 18 XFDDCS 34 XFDDCS X48 28 xFoccs OF XFDCCS x4C 38 a xrsccs O48 XRSCCS 2 76 11D 113152719 111315517 19 xprtcs O4 4 XPRTCS 2 2F 156 XPCR 23 25 28 29 31 33 XCALDCS os XCALDCS X5F XWRITE GATE 39 PCLK OT PCL K X4D X3D PCLK RSCLK OTF RSCLK 2 7C LS367 2 72 xTc Oo XTC X4C X3D DREQ...

Page 255: ... DOS DATAS eTsf__7s1s0r DATAG x9G XRSCCS DATAT ETXD X44 XSTPDT 1 3C XXxI xeDT 1 3C XXIOR 1 3D RSCLK 1 3C DBI DBO 1 3B 0B7 0B2 XCDR RCDT RCDR X40 XPLBGI ERXD ECTS 1 3B D04 p00 XESTB XEAUTOFDXT EDSR XEINIT XESLCT IN EDCD 1 34 005 X4A XSTPCD PGATE X4H RI 1 3C XRESET 1 3C 5V 1 3C R22 1 38 3 68 EAB 8 4 7K SOO 1 3B 10 g 10A X4A XPLBG2 GND 1 38 l 3D X PRTCS XPRTCS I K2A 3 LSse S00 iu 3 O OO ee oe 2 ion 2...

Page 256: ...G 500 EAB IS Oo XIOW X4D 14 13 L7 DREQ3 X26 of 4 XMEMR X4D 4 OSC g 12 104 ut EFOSC XEIOR 4 12V 22 1Op xX x OTSORMEMW OX SED iev Om i4 318i8mHz X8D x50 ETOW 12V O AEN X4E 7 XEMEMR o 4 XEXDACKI X 4E LS244 XEMEMW o 22 XEXDACK2 X4E X1OR XEIOR X8D X4H a bp X5D ECLK 30 Ww KEIOW X8D X7D EOSC _ oO XEXDACK3 X4E X MEMR XEMEMR X8D X4H ov o EXDB7 X4E FG X5D ETC 45V 5 E x2p XMEMW XEMEMW X8D O EXDB6 AEN EAEN X8...

Page 257: ...ufactures to be used for replacementin critical circuits Ref No Parts No Parts Name Description w o z Remarks Ref No Parts No Parts Name Description Remarks 1 YJJ7012680B4 Operate Lavel 1 2 YJJ8C07550B2 Pad 1 1 3 YJJ8CO7560B2 Pad 2 1 4 YJJ8B07540E3 Inner Carton 1 5 YJJ8D07580B3 Diskette Wrap 1 6 YJJ8D08020B4 Accessory Pad 1 OL SHTYOSSHOOY Ppue ASWO ONIMOVd ...

Page 258: ......

Page 259: ... NO seal Operate lavel User Manual Accessory Pad DOS Manual System diskette Reference Manual Polyethylene bag Polyethylene bag l a AC cord Polyethylene bag N 4 Main body PAD 2 3 PAD 1 Inner Carton It L5l ...

Page 260: ...ORDER NO DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit ll PlasmaDisplay Unit IV Keyboard V Power Supply Unit VI Floppy Disk Drive Vil Option Panasonic Meeeneeeie ...

Page 261: ......

Page 262: ...le 53 8 Hz Input foutput signal level TTL level Power consumption 34 W max Characters and graphics can be displayed in specified size by inputting TTL level vertical and horizontal sync signals 4 bit data signals and data transfer shift clock signals The brightness can be controlled by the external potentiometer Power Supply Voltage Current Capacity max V for IC 5 V 0 25 V O 6 A VI for IC 195 Vv 5...

Page 263: ...ck or break the edges Also take special care with the vent tube that protrudes from the rear of the glass container Install the unit with enough clearance to ensure good ventilation Protect the display unit from impact and extreme pressure Do not expose the display unit to strong electrostatic charges III 2 ...

Page 264: ......

Page 265: ... sv OPpto 320 Bit Shift Register isolator 320 Latches Y LIne Timing Generator VR 5SOKQO Brightness Control X Driver X Driver KOT 1 KOT 2 Y Driver 320 Latches 320 Bit Shift Register Buffer Driver ADOT Figure 3 1 Display Unit Block Diagram WWHOVId MOOT ...

Page 266: ...re 4 1 Structure of Display Panel The structure of the panel is shown in Figure 4 1 640 transparent Y electrodes are arrayed vertically on the front glass plate while 401 X electrodes are arrayed horizontally on the rear glass plate The uppermost X electrode is a reset electrode and the remaining 400 X electrodes are display electrodes Also on the rear glass plate partitions are installed The peri...

Page 267: ...system unit The Signals Vsync and Hsync are converted from TTL level to a 200 V level by an optoisolator Scanning signals Si CLK INV1 and INV2 are generated by an X line timing circuit These signals are connected to the scanning circuits installed at the left and right of the display panel DATAO through 3 and SCK are directly connected to the display circuit installed at the top and bottom of the ...

Page 268: ...during which all the X lines are OFF are provided within the respective horizontal scanning periods tHn 1 tHn During these periods the charge CHG forcibly switches the output transistors of the Y drivers to ON and charges the auxiliary discharge capacitors installed on each of the Y lines in the display panel Then if for example Xn is switched ON when the latch output connected to Ym is L LOW the ...

Page 269: ... ch ch ch dych a RA x q Ly s Wy g Ld NN CIN cy Ama Mc oT YS 1 ft 4 OTT ND WITT Ta oa NX _ 4 Momma mamma aza AY YY YY fAnVabWahwshwabVsnvsbhvah WW YY YP Woy Ma VOW LINENS THOT 4 I I f 1 3 i N Cc MWcpy WYWYy aK aw Lv DY anand Ivy Q SOO aaaa _s TT OmMmM om we D y VU py Oddo Pryy CETtEryt Ta Tt ad ra i Z NS i i X398 Vv 200V Cc CHG T TI p INV I 20i Bit Shift Register pb SI t t t gol lis 320 Latches 320...

Page 270: ...Vsync rs yne ee ee ee ee 7 5 6ys M3 Yt 74 5 ys Ic5 3 A 4 5ys SN fr Sf L ff 195vV x1 r _S Pr ZIOOV Ne S 195V a Figure 4 3 Timing Chart III 9 ...

Page 271: ...107 G3 ISus M10 CL rc8 77777 71 VILLILILLLLLLLLLLLLA_ V Bright Control 37 50s a _ ts rea ssw SI rn a 4 531 M6 19O0V rc4 I95V 7 y Display _ 100 Brigtness 5 oN 7 Ym wer ey 60V S eee z 95V xn 1I195V I Figure 4 4 Operation During Horizontal Scanning Period III 10 ...

Page 272: ...DATAO through DATA3 to Y line shift registers Enable ENA H Ordinary display L No voltage applied to Y lines Input Circuits Vsync Hsync DATAO to 3 SCK ENA 5 V 10KA LSO4 5V lOKN LS 123 Figure 4 5 4 5 Notes 1 Connect the 205 V 205 V and 5 V 200 V power sources to J2 in the floating state 2 The output stage of the optisolator of BDT the X line timing generator CN3 CN4 KDT 1 and KDT 2 are high voltage ...

Page 273: ...it 4 Move Keyboard D and all optional units away from working area 2 f Figure 5 1 Step 2 Removing Rear Upper Cover 1 Press down on thumbsets B of C Rear Upper Cover C and unlatch A claws inside Lift Rear Upper Cover C up from Upper Case Wei SS Ss Rear View Side View co Cc r B Figure 5 2 Step 3 Detaching Display from System Unit 1 Detach Earth Cables A from System Unit 2 Remove mounting screws B 3 ...

Page 274: ... B Remove retaining screws C Push cables D in direction indicated by arrows Turn over Display with screen up Unlatch side claws E Note To unlatch side claws grasp both edges of display cover and pull out until the inside claws appear Slide Display Unit A and Display Cover B in direction indicated by arrows III 13 ...

Page 275: ...Slide hook B in direction indicated by arrow 3 Remove lever C 4 Grasp hook B and pull up in direction indicated by arrow then unclip from Display Unit A 5 Remove Spring from lever C 6 Remove Lock Button Step 6 Plasma Figure 5 6 1 Remove mounting screws A 2 Disconnect connectors B III 14 ...

Page 276: ...drawing on attached sheet for detail b connector the attached sheet Installation Procedure Insert the flat cables 2 into the specified connector of the buffer a driver bob Fasten the buffer driver with screw 2 Flat Flat 1 Cabl 1 Cable 1 Cable 2 Flat Cable Screw 1 Screw 2 Screw 2 1 Buffer Cathode pe 1 Screw 1 Cathode Driver 2 Driver 1 T 4 Ca C __ _ 1 i Plasma Display Panel iL Do not remove screws 1...

Page 277: ......

Page 278: ...2 Connect KDT checking connectors with CN3 and CN4 Specified X line is not displayed q Connect KDT checking connectors with CN3 and CN4 specified X line Check Din Pin 25 26 ICl to 10 Dout Pin 24 25 IC1l to 10 CLK Pin 31 IC1l to 10 and drive output of driver IC corresponding to Plasma Display Panel Replacement from driver IC correspond Is output ing to specified X line normal Specified Y line is no...

Page 279: ...rmal board and CN2 BDT Yes No IC7 Remove CN3 and CN4 IC10 Check and connect J2 Check out No put siganl BDT of main board Icl Check Connect CN1 IC6 l ves ADT 1 BDT icl Check iclO 1 Si Connect CN3 Is X driver No CLK output normal Invi Check KDT 2 INV2 icl Connect CN2 Yes icl0 Check ADT 2 __ icl ts No CL icto Check Y driver input CHG Check Signal normal STB KDT 1 Yes icl e10 Check Fault in display pa...

Page 280: ...REPLACEMENT PARTS LIST AND DRAWING Exploded View 7 1L Display Sub Assy Figure 7 1 Plasma Display Unit Exploded View i i a a Driver PCB Ass TItI 21 ...

Page 281: ... 1 YJJDK02570B4 Plasma DC Cable 1 3 2 YJJUX03340B3 Softner L 1 3 3 YJJUX02850B4 ARM L 1 4 4 1 YJJDKO2560B3 Plasma Signal Cable 1 4 2 YJJUX02840B4 ARM R 1 4 3 YJJUX03330B3 Softner R 1 5 YJJ4035180A4 Detector Cable 1 5 1 YJMQS 1AU pe Switch 1 5 2 YJJDKO2590B4 Detector Cable 1 6 YJJ4J01280B4 Spring 2 7 YJJ6D08500B3 Plasma Hook 2 8 YJJ4R01230B4 Hook Cover 2 9 YJJ5R08510B4 Look Button 2 10 YJJ3005950A4...

Page 282: ... pennnnnnnnn onBeata A ie LL LL 4 o Le wo Anode Driver IC x 0 Anode Driver 2 Heldee fh Driver Holder ADT 2 Ja Anode Driver IC o Anode Driver 1 node Pri 10 2 oS aor 1 o CS uu LL PJ LIL Cathode Driver IC Cathode Driver IC x 7 x 7 Resistor Module x 4 1 Do not remove screws Figure 7 2 Plasma Display Panel Rear Side COL zeatisaq pue Aetdstq eusetd ...

Page 283: ...Tift VC Figure 7 3 Buffer Driver Eeenna Parts Layout ...

Page 284: ...O CN Pin No Wire Color 1 Red 2 Brown Figure 7 4 Bright Control Cable Figure 7 5 Plasma DC Cable CN Pin No 2 CN Pin No Wire Color Signal Name 1 1 Red 5 V 2 2 Yellow 200 V 3 3 Brown 195 V Figure 7 6 Plasma FG Cable III 25 ...

Page 285: ... 4 GND Brown Black Spiral 3 5 HSync Black 4 6 GND Gray 5 1 DATAO Purple 6 2 DATA1 Blue 7 3 DATA2 Green 8 4 DATA3 Yellow 9 5 GND Red 10 7 GND White 11 7 SFTCLK 12 NC NC NC White Black Spiral 13 1 5 V Yellow Black Spiral 14 2 5 V Brown 15 8 GND Orange 16 6 ENA Figure 7 7 Signal Cable TII 26 ...

Page 286: ... ECKF1H471JT C Capacitor 8 CT1 ECQV1H104J2 F Capacitor 1 C1 2 7 ECSZ16HS10 Tanta Capacitor 3 J3 EMCS0251 ML Connector 2P 1 JIA EMCSO751ML Connector 7P 1 J1B EMCS0851ML Connector 8P 1 R1 ERD25TJ103 C Resistor 1 R4 5 ERD25TJ224 C Resistor 2 R2 3 ERD25TJ273 C Resistor 2 R6 7 ERD25TJ472 C Resistor 2 RA3 EXBD84371S Resistor Array 1 RA4 5 EXBD86372S Resistor Array 2 RA6 EXBD88373G Resistor Array 1 RA1 E...

Page 287: ......

Page 288: ... __ s eke 195v orf a a 95V RAS OTK 5 RAG 5V 9 ofS Re 3 r2k VRI 47k RI vs oO 6 Mm AMe 10 li2_ _R6 sr7j ics UL 2 vR2 OK rn 5V CTIO 4 7K 34 7K C4 1Ou 5V 2 gf Ite3s00P i RAI C828 4 TL7700 p DA 3 A 9 Ice DA3 4 _ ond MIO SCLK 5 s OQ RA LENA 3 Oh a 2 CT RAS cts Ras crs RAS stp 6 q i LS123 470P 470P 470P CHG 7 2 V4 X 2 alt ef Te ia lis 3 8 RAZ 9 7 IC 7 3 6 4 7K my 5 BRAl 5 BRA2 cq Ics rat IC 4 IC 10 _ GND...

Page 289: ...alainys iC iC1iO SN751508 Y639 Y577 YS75 S SOY513 Y5l1 Y481 Y479 Y449 Y3I9 _ SsiY257 Y255 _Se OS S CSOY IQ YI9SI YI61 YI5S9 YI29 Figure 7 9 Anode Drive Circuit Diagram ADT 1 Y447 Y385 YI27 __ Y65 Y383 OE 32 Tit 31 ...

Page 290: ... SCOY5 12 Y446 S Y 384 Y382 _HSem sC 3200 iC iclo SN751518 _ ae eee eee oe oo oe ewe ee ee one me _m ae ame see co cme e em ee oa ase ow Y3i8 Y256 Y254 _ Y192 YI9O0 YI60 YI58 Y128 Yi26 _ Y64 Y62 Nem YD Figure 7 10 Anode Drive Circuit Diagram ADT 2 Til 33 ...

Page 291: ... O OKA KHV O KK X255 0 0ly X2 2 3 4 5 6 7 8 X317 X319 X38 X383 X399 Figure 7 1 Cathode Drive Circuit Diagram KDT 1 III 35 ...

Page 292: ...X254 O Ol yx 2 COryl MP ATE Gp X316 X318 X380 X382 X398 Figure 7 12 Cathode Drive Circuit Diagram KDT 2 ...

Page 293: ...1 oo 14 13 Co ls 17 Cc I 16 ne Co J xc Guo 4 J cnxo xc Co J xe xc Co chk Co oove Veco Co C Vee NC NC ou Din Pout J RS b SN751516 Pin Assignment HVOOL of Hv032 902 Co 03 Co 30 04 Co 23 60S COO 28 606 Co 7 607 COO T 26 08 Co J 25 09 Co 1 24 elo Coo 9 23 1 Co p22 12 Co J 2h 13 cs S sN751S5 16 20 14 Co p is 1s Co Rts 16 Co pi 1 Nc s 3 NC Gnd Co _ s anp Ne CIT NC zeE Re Ne CO Cs CLK Vee J _____ Vec nc ...

Page 294: ...nd Cc Ine Nc Co T cu Ls Nc nc Co cux Vec Co J vee Din2 bout2 in outl D 1 _ d SN751508 Pin Assignment HVO32 Co J v001 31 3 02 30 Co 03 23 CT Sis 8 28 Co OS 27 Co _ 06 26 Co 07 25 Co _SCi s COB 24 CT S 09 23 Co _ 10 22 Co ll 21 Co 2 20 Co SN751508 H 3 19 oS 14 18 CoS 1 17 oS _ 16 cuno Co J cup Nc Co CHG CoS Ne Nc Co po ts CLK 7 i NC vee Co J Vee Dout2 Co Din2 Douth Co F inl III 40 ...

Page 295: ...b Circuit Configuration XD Nn a ol a b O _ W 9 c Constants and Ratings Element No Ry R R Ry Nominal resistance 47 kf 15 k2 15 k2 10 kX Resistance tolerance 10 23 Rated power for the element 1 8 W d Shape Dimensions and Marking No l pin mark TIT 41 ...

Page 296: ...3 R5 6 2 3 4 5 6 7 8 c Constants and Ratings Element No Ri R R Ry Ry Re Nominal 220 2 220 2 4 7 kQ2 14 7 kQ 4 7 kQ 4 7 kQ resistance Resistance 59 103 tolerance Rated power for the element 1 8 W d Shape Dimensions and Marking No l pin mark eD3 72 5 III 42 crs aoe a ...

Page 297: ...5 Re R7 R7 2 3 4 5 6 7 8 c Constants and Ratings Element No R R R Ry R Re Ro Re Nominal 330 k2 1100 kQ 12 kX 12 KR 12 KA 112 KR 27 kA 12 7 KL resistance Resistance 56 tolerance 2 Rated power 1 8 W for the element d Shape Dimensions and Marking No l pin mark TIT 43 ...

Page 298: ......

Page 299: ...DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit ll Plasma Display Unit IV Keyboard Vo Power Supply Unit VI Floppy Disk Drive VII Option s e i Panasonic _ MatsushitaElectricTradingCo Lt ...

Page 300: ......

Page 301: ...Buffer Size 16 bytes Detachable Yes National Versions ASCII English Swedish Finnish French German Controller uUPD8048C One Chip Microprocessor Connector Pin Assignment Table 1 1 Pin Assignment Pin No Signal Name Signal Type 1 KBDATA INPUT OUTPUT 2 KBCLK INPUT OUTPUT 3 HARD RESET INPUT 4 GND POWER 5 5 V POWER 6 FG Shared with the GND line Iv 1 ...

Page 302: ...re Figure Figure 2 3 ASCII S English Swedish Finnish French German For keys with two different characters on the keytop refer to the example below 3 Press this key alone Press this key together with the SHIFT key The 16 key numeric keypad is standard for all versions 4 HAE em NY Scroll Lock Break OIC CI 4 Ctri ARC 9 PgUp n n n 8 a o a aa aa PgDn FILE S 7 v Ait t IU Caps Lock Figure 2 1 ASCII Versi...

Page 303: ...v vl mal al N on Figure 2 2 English Version Swedish Finnish Version 2 3 For keys that have three or four different characters on the keytop refer to the example below SHIFT SHIFT Alt Press this key alone po Press this key together with the SHIFT key i Press this key together with the Alt key Normal _ _ Alt _ Press this key together with the SHIFT and Alt keys A 1 2 3 4 5 6 7 8 9 Oo ae ALL PW ES TU...

Page 304: ...5 y PgUp 7 mn n n nT y W X C V N a bi cn s F H G H J WH K L eg u He PgDn ie 2 9 Caps Lock on 8 Ft Le II NO uw Figure 2 4 French Version German Version For keys that have three different characters on the keytop refer to the example below Press this key alone Press this key together with the SHIFT key l Press this key together with Ctrl and Alt keys Ctri l if ri Alt Esc s o 1 2 3 4 5 7 8 9 B wo aae...

Page 305: ... CN1 y CN1 Micro processor KBDATA INT rae Interface oes PIO P27 KBCLEK TO Interface Pil H R Interface emRES OBO LED Driver hel p15 P12 No 81 087 LED Power j Suppl Driver PP Y P13 paer j 3 No 17 X 1 X2 e 45 V pe GND The operation at each stage is Figure 3 1 Block Diagram IV scan J Driver _ Key Matrix peo _ _ 2 _O Ceralock ...

Page 306: ...cy divided into a fifteenth The resulting 400 kHz appears at pin 11 of the microprocessor Figure 4 16 Scale on the abscissa 1 us div TL Figure 4 1 ALE Waveform This microprocessor operation can be checked by observing this waveform Data Type and Logic G KBDATA Data output signal from the keyboard Positive logic BUSY input signal from the system unit Negative logic Oo Data type ON code Key data out...

Page 307: ...t Negative logic 4 4 KBDATA and KBCLK Output Timing Both signals are bidirectional and transfer data between the system unit and the keyboard under the following conditions 1 When KBDATA H and KBCLK H at the system unit Scale on the abscissa 0 1 ms div Top KBDATA Bottom KBCLK Figure 4 2 KBDATA and KBCLK Outputs Key ON OFF Ly Ly 1 t 30 ms max ty to 1 t 30 ms max H 2 KBDATA TZ Figure 4 3 KBDATA Outp...

Page 308: ...Pll Figure 4 4 shows the timing of KBCLK and KBDATA t 3 4 I 1 _ TYPpUDUYYPUD Wo ct KBDATA t 2 Start LSB MSB Stop Bit Bit Make 0 1 t 9us Break 1 1 t 22 Us t 31 Us ty 103 Us Figure 4 4 Timing of KBCLK and KBDATA A unit of data from KBDATA consists of a start bit and 8 data bits followed by a stop bit The 8 bit data is arranged from LSB to MSB As Figure 4 5 shows KBDATA output is inhibited for 6 ms a...

Page 309: ...ut data to KBDATA it stores the data in the buffer 16 bytes ona first in first out basis Output Routine Outputs the first clock Start bit KBDATA L H Outputs the Stops CLK and items described stores data in in 1 buffer Scans and attempt output from the buffer at 6 ms intervals 1 Figure 4 6 Output Condition it x Iv 9 ...

Page 310: ...he Unit Keeps 1D rot The Level Low Ld Start Bit A Figure 4 7 Sequence When KBDATA L and KBCLK H When the buffer overflows FF HEX Is output at the 17th byte of the buffer When KBDATA H and KBCLK L at the system unit When the system unit holds KBCLK to LOW for 67 5 ms or more the keyboard performs self test See also the section entitled Self Test IV 10 ...

Page 311: ...a matrix composed of a scan driver and a scan detector DBO DB7 of the microprocessor A low active signal is output to the key matrix to detect which key is depressed in the corresponding line Signals are output directly from the microprocessor to the driver The output intervals differ slightly depending on whether or not a key is pressed Figure 4 9 shows an average output interval Scale on the abs...

Page 312: ...ircuit diagram goes low In Figure 4 10 for example the space key is pressed while a in the circuit diagram Section 9 is being scanned Scale on the abscissa 2 ms div aaET aNCRIN Top Microprocessor en P24 output Bottom Microprocessor aE INE Pa a P25 output Figure 4 10 Scan Detector Line 1 Line 2 i Line 10 Line 11 Figure 4 11 Scan Driver Output As Figure 4 11 shows a low active signal is output from ...

Page 313: ...its DBO DB7 of the microprocessor corresponding to the key thus determining which key is being pressed Y ___ of oN scan A C_ rT Driver D t CI f ft vw ay wry y Ty Micro pro cessor DB 7 Figure 4 12 Scanning As Figure 4 12 shows when key A is pressed and line on the X axis is scanned the line 2 on the Y axis goes low The microprocessor then detects that scanning lines and 2 are low and determines key...

Page 314: ...e key being pressed is released the repeat function is terminated ON Key 1 OFF wom t LIC ON 0 1 1 I 30 ms max ON To 0 55 s 0 05 s Tt 100 ms 10 ms Figure 4 13 Start of Repeat Function The key last recognized as ON is the key that effects the repeat function ON Key 1 OFF ON Key 2 OFF ona SL JL Key 1 Key 1 Key 2 Key 2 ON Data ON Data ON Data ON Data Figure 4 14 Repeat Shift Iv 14 ...

Page 315: ...1 ms or more Figure 5 1 shows the timing of a self test reguest KBCLK Ist Byte in the Self Test Result 2nd Byte in the Self Test Result fF i a 40 ms or more r 4 r 4 KBDATA fl t 10 ms max Approx 0 7 Ss Output Data by Ordinary Scan Figure 5 1 Self Test Request Q When KBCLK L continues for 1ms or more after it becomes LOW the self test request is accepted 2 When KBCLK L does not continue for 1 ms the...

Page 316: ...5 2 Self Test Flowchart Start ROM RAM No Check OK Outputs AA HEX Outputs 55 HEX LED Indicator ON LED Indicator OFF Initializes flags memory and port L Oe Figure 5 2 Self Test Sequence IV 16 ...

Page 317: ...main power switch A to OFF 2 Unplug AC power cord B from outlet 3 Disconnect all cables AC Power Cord B Keyboard Cable C and all optional unit cables from System Unit Step 2 Removing Screws Figure 6 2 1 Press keyboard A with back side up 2 Pull up retractable legs B 3 Remove screws Cl IV 17 ...

Page 318: ... then pull apart to expose inside claw Return keyboard to upright position and lift cover C up from keyboard base D Step 4 Removing Keyboard Assembly A A D A Figure 6 4 1 Remove screws A 2 Remove reinforcement plate B and pull up keyboard assembly C from keyboard base Note Keep reinforcement plates B and D in safe place Reverse steps for reassembly IV 18 ...

Page 319: ...t a new key top on to the key switch Compare the key top height with other key top heights and check that it fits tightly Key Top Key Switch Figure 6 5 b 2L Key Top 1 ii iii Remove the key top from the Key switch Hook the wire into the wire holder Put the key top on the key switch Check that the key top fits tightly Key Top E Wire Figure 6 6 Iv 19 ...

Page 320: ...op Guide Pin Coil Spring Guide Figure 6 7 i Remove the key top from the key switch ii Hook the wire into the wire holder iii Put the key top into the key switch Check that the key top fits tightly Note Be careful not to allow the coil spring to jump out IV 20 ...

Page 321: ...lder 6 points on the rear Side Remove a key switch Insert the new switch unit and solder the six points Insert the key top on the sliding body as instructed in v and vi of 1 a LED Indicator Remove the key top as instructed in 1 and ii of 1 a Remove solder at 4 points from the reverse side and pull out the key on the front side Insert the new switch unit and solder the four points Insert the key to...

Page 322: ...utput Microprocessor Check Pattern if Output Waveform is not Available Check Output of IC Note 3 Found Repair Shorted Connected to Microprocessor Check for Short Location Scan Output Check Pattern if 4 No is Mad me Output Waveform Microprocessor or Output 1s Made is not Available P Ic Connected to Microprocessor is Defective Press Keys and Check Microproces sor Input Note 3 Matching the Matrix Rep...

Page 323: ...s Output Check Pin 1 of Micro processor No Level is High Check if Clock Pulse is Out put Clock No Pulse is Output Check for Short and Wire Breakage to Connector Section Yes Recheck from Beginning No Repari Short or Wire Breakage Note See the circuit diagram Figure 7 1 Troubleshooting ...

Page 324: ... ICD Wire Brekage of QO2 or R14 QO2 or R14 is Defective ICD is Defective Repair Wire Breakage Check Pin 27 of Micro processor Data is Out put Check Pin 10 of ICD Data is Out put R17 is Defective Figure 7 1 Troubleshooting 24 Microprocessor or ICD is Defective ICD or R17 is Defective ...

Page 325: ...cro Clock Level is High processor is Pulse is Microprocessor Defective Output or ICD id P Defective Check Pin 2 Check Pin 2 of ICD of ICD o ICD is Clock ICD or R19 Defective Pulse is is Defective Output Repair Defective Ql is Defective Figure 7 1 Troubleshooting IV 25 ...

Page 326: ...ocessor processor has low input more Check than 50 ms None for Breakage and Short Control by Unit is Abnormal Repair Broken or Yes Shorted Pattern More than 50 ms No Check Pattern C Check after Connected to Confiriming Pin 4 of Microprocessor Microprocessor Scan Output Control by Unit is Abnormal Repair Broken or Shorted Pattern Figure 7 1 Troubleshooting IV 26 ...

Page 327: ...6B REPLACEMENT PARTS LIST AND DRAWING 8 1 Exploded View Figure 8 l Keyboard Unit Exploded View Wty IV 27 ...

Page 328: ...KFLAFOOOA Push Switch LED 2 4 5 YJ21K FOO8A Lever 5 YJJ3B10260B3 Reinforcing Plate 2 1 6 YJJU X03300B 1 Lower Case 1 7 YJJ5V08620B4 Pad 2 8 YJJSNO8560B3 Tilt Leg 2 1 2075K Diode 85 A UPD8048HC169 Lsi 1 B SN74159N ic 1 C SN74LS132N ic 1 D SN7417N IC 1 Ref No Parts No Parts Name Description Pes Remarks Set CERA YJKMFC1005T1 LOCK Crystal Oscillator 1 R14 15 ERD25TJ271 Carbon Resistor 2 L702 1 4W R10 ...

Page 329: ...23 YJ86N 1044024 YJ86N1C44025 YJ86N 1044026 CTO W NOM TVAKHWHNGQ YJ86N1C44027 to o YJ86N 1044028 YJ86N2C44013 YJ86N2C44014 YJ86N2C44015 YJ86N2C44016 YJ86N2C44017 YJ86N2C440 18 c A DM Ss PD YJ86N2C44019 YJ86N2C44020 YJ86N2C44021 YJ86N2C44022 YJ86N2C44023 YJ86N2C44024 YJ86N2C44025 YJ86N2C44026 YJ86N2C44027 YJ86N3C44014 YJ86N3C44015 YJ86N3C44016 YJ86N3C44018 YJ86N3C44019 YJ86N3C44021 YJ86N3C44022 YJ8...

Page 330: ...J81CHC44001 ons 1 ins YJ86N4C44025 PgDn 1 YJ81Y6CCA rape 1 YI81W4C44001 Del YJCBKFOQ0A Sera 1 YJ86N1C25058 F1 1 6 YJ86N1044035 3 1 Germany YJ86N1C25059 F2 1 YJ86N1C44036 3 1 YJ86N1C25060 Esc 1 YJ86N1C44037 6 1 YJ86N2C25018 F3 1 j YJ86N1C44038 d 1 YJ86N2C25019 F4 1 YJ86N1C44039 3 1 YJ86N2C25020 _ 1 1 YJ86N1C44040 5 YJ86N3C25036 F5 1 YJ86N1C44041 YJ86N3C25037 F6 5 1 YJ86N1C44042 YJ86N3C25043 1 6 1 Y...

Page 331: ...45 7 TY cinish YJ86N1C44063 1 YJ86N 1044046 1 YJ86N2C44033 ve L 1 YJ86N1C44047 iB 1 YJ86N2C44034 1 YJ86N1C44048 is 1 YJ86N2C44035 A 1 YJ86N1C44049 1 YJ86N3C44030 Q 1 YJ86N1C44050 5 1 YJ86N3C44031 M 1 YJ86N1C44051 1 YJ86N3C44040 1 YJ86N1C44052 ot 1 YJ86N3C44041 1 YJ86N2C44031 A 1 YJ86N4C44035 1 YJ86N2C44032 7 3 1 YJ86N4C44036 1 YJ86N3C44037 BS 1 YJ86N4C44037 1 YJ86N3C44038 A 1 YJ86N4C44038 1 YJ86N4...

Page 332: ... 3D 3E OF 10 11 12 13 14 15116 17 18 19 1A 1B 47148149 4A 39 40 4 42 43 44 45 4el 47 as agi sq 51 52 53 Sal 55 Sel 57 3F 40 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 1C 4B 4C 4D0 4E 58 59 6o 61 62 63 64 65 cel 67 6s 69 70 71 72 74 74 7s vel 84 41 42 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 4F 50 51 77 78 79 80 81 82 83 43 44 38 39 3A 52 53 1C Figure 8 2 Coard Table C 8 aTqeL preood ...

Page 333: ...AGRAM 8048HC 169 Vcc P24 P25 P26 P27 CERALOCK FBI 5 Volts 5 Zz Cl C9 O 1y C5 ea OOP Oly 47 l Q Ground 4 4 7K x8 R ARY JP FG 6 R15 2700 Frame Ground Keyboard Dota NO 8I R14 2700 Keyboord Clock 2 NO 17 RESET 3 Figure 8 3 Circuit Drawing IV 33 ...

Page 334: ...NO DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit ll Plasma Display Unit IV Keyboard Vo Power Supply Unit VI Floppy Disk Drive VII Option 2 Panasonic _ MatzunhiteElectricTedingCo Lt ...

Page 335: ......

Page 336: ... V 10 mA 260 mA 1 205 V plasma display 10 mA 150 mA 1 200 V plasma display O mA 60 mA Note 1 When the power supply is connected to the equipment the 205 V becomes 200 V and the 200 V becomes 195 V respectively Input Voltage Switch Selectable 50 60 Hz 220 to 240 V 10 10 50 60 Hz 110 to 120 V Input Consumption 220 V 1 4 A max 110 V 2 A max Fuse Europe standard BET 5A miniature fuse ...

Page 337: ...2 APPEARANCE Option Boards Hard Disk controller JB 3305 only T PSU f FDD JB 3301 HDD JB 3305 an Z Z_LN 1 O Board I CPU Board Voltage Select Switch Fuse ...

Page 338: ...a 5 V 7 L Output Circuit Line Filter Circuit Rectifying Smoothing Circuit 5 V Output Circuit Primary Secondary Control Control Circuit Circuit 12 V Output Circuit High Volt Converter age Output Circuit Circuit for Plasma for Plasma 4 V Y Output Circuit for Plasma Driver For Plasma Primary Control Circuit Pe Secondary Control Circuit AAA VV YV o Figure 3 1 System Block Diagram VY ...

Page 339: ...an be used Also an erroneous input voltage i e an input of 230 V at the 115 V setting simply blows the input fuse the main body of the power unit is protected Reinforced insulation is employed for parts such as transformers photocouplers and printed boards which require insulation between primary and secondary circuits Input Block F 250 VAC SA 2 L435 Wr N 21 VAAS ae eb nm O WN st t Toot oO J OC a ...

Page 340: ...V input and full wave rectification for 230 V input When 230 V is applied at the 115 V setting the arrester AR1 is discharged and melts the fuse Fl protecting the converter circuits To restore this unit to normal set the input voltage and replace fuse Fl The arrester AR1 is separated from the circuit by the 1 circuit of the selector switch SW1 when the input is set for 115 V TH40 F3 and R43 compri...

Page 341: ...ed from the secondary winding of transformer T40 The 5 V output voltage is sensed and regulated to a constant value 12 V and 5 V outputs are stabilized by Voltage Regulator ICs The Voltage Regulator ICs stabilize 5 V and 12 V outputs Converter and Output Circuits for Plasma As in the case of the low voltage output a flyback converter circuit is employed for the plasma The 205 V output voltage for ...

Page 342: ...4 Sts i2v R8O Rj8 CN3 PCBX 51S 5V coo i2Vv 6 eels lov aa Figure 4 3 Converter and Output Circuit D3I Ic 31 CN5 POP 7 p 200Vv TI40 c3ing 5 R36 C32 5 6 lio SR221 L 4 D2i I i D22 R150 C180 r Ji2 c2imz coom C46 Ty Woe R149 DI40 cols Pp WA 7 4 0 LZ ls 205v 1 LJ Ici 1 CN1 FDDI DZ141 4 _ tf RIBO I 12V C14 RIS3 316 7 ciiog 3 4 ci3g 5V C12 2f as DiI 33 Lh o rs OV R41 R40 mn Figure 4 4 Converter and Output ...

Page 343: ...tion type with ON period control These circuits control the timing of the absorption by IC40 and IC140 of the drive current from the base drive windings of transformers T40 and T140 The control signals are transmitted from the secondary side via photocouplers PCO1l and PC21 IC40 and IC140 also have built in surge current protection functions c8so0c R8O Qi40 Lo wD o o b DZ 41 Pic2i Figure 4 6 Prima...

Page 344: ...nt change creates a current flow in the photocoupler PCO1 diode and transmits it to the primary control circuit Figure 4 8 shows the secondary control circuit for the plasma The principle of operation of this circuit is similar to that just described above 2 t it ee T140 cola 3 R3 6 io y R22 4 D2 PtH p22 3 2 coins 2 Oo Figure 4 7 Secondary Control Circuits for Low Voltage 15 LO y DO a r a wrwn e I...

Page 345: ...adjusting RVO1 The voltage at the connector point of the 200 V plasma output is set at 205 1 V by adjusting RV20 WARNING Plasma output is shown below Be sure to measure the voltage between the V and V terminals and adjust to 205 1 V po 5Vv _ eS Rzx _ X _ a ce 7 Psu GND gee eee Ol L_ Piasma Ponel Voltmeter i fy Red O ae tvYi 4 j O Yellow _ svi O Brown _ xvVI Lee _ Though the voltage between V and V...

Page 346: ... by a new one except a blown fuse failure at each service station The defective power supply unit must be sent back to our factory When replacing blown fuses on both AC input primary side and 2 DC output secondary side of the power supply unit be sure to use Matsushita s genuine spare fuses pees WARNING This computer uses some particular parts for safety and protection They are given international...

Page 347: ... or Col Replacement defective No Yes Is Q40 defective Replacement Q40 Notes 2 and 3 No Cis Q140 defective NOTES 1 When replacing fuses use Matsushita parts with proper ratings T Replacement 9140 Notes 2 and 3 2 Transistor destruction occurs when the feedback operation from the secondary side circuit does not work Therefore the secondary side circuit and the photocoupler feedback circuit must also ...

Page 348: ...tput or No Plasma Output M N N O o low voltage output r no plasma output J 4 YN ZN No Is any output shorting Are IC40 and IC140 No normal Sf i Are PCO1 and PC21 IN No normal V 13 Repair the short circuit Replacement Replace ...

Page 349: ...00 V is not output f Crs the 200 V output short circuited No No Is the IC31 normal Se Replace the IC31 f Yes N Is the D31 normal yee Replace the D31 12 V is not cutput Is the 12 V output short circuited Correct the short circuit No Is the IcCl1l norma See Replace the IC11l Yes No Is the Dll normal Replace the D1l Yes Correct the short circuit WN OS 12 V N NC ...

Page 350: ...he short circuit 5 V 5 V is not output f Yes Is the 5 V output short circuited Correct the short circuit No 12 V 2 V is not output 1 Yes Is the 12 V output short circuited Correct the short circuit No No Is the IC32 normal ae Replace the IC32 Yes N Is the D32 normal Replace the D32 No Is the IC33 normal Replace the 1C33 ...

Page 351: ...nge 1 1 Red 2 Z Black 2 2 Yellow 3 3 Black 3 3 Brown 4 4 Red CN3 CN4 CN3 CN4 PCB side CN side Wire PCB side CN side Wire color color Pin No Pin No Center Pin No Pin No Center 1 1 Black 1 3 Orange 2 4 Orange 2 1 Black 3 5 Black 3 5 Black 4 3 Red 4 2 Green 5 2 Red 5 4 Blue NOTE CN No is shown Power Supply Unit Parts Location V 16 ...

Page 352: ...REPLACEMENT PARTS LIST AND DRAWING Exploded Drawing 7 1L Figure 7 1 PSU Exploded View V 17 ...

Page 353: ...go S A 4 cai e R f N ve C5 3 st D140 Tt FLT CS E C40 ss Oa oO Oo o S O R p46 Rae lan i NY P850470 U RVO er Roz_t cm 1 cna 2 mek 3 46 C4 aa OnE 6 C46 gay o 1 TD co7 9 10 PO mol 8 oot SE C Yr80 if 4 i 42 a rar 240 c510 E le t R53 R49_R50 COs S e a ny R42 TT ko co3 3co0 9 40 5 Y 060 rs 0 R61 a tJ REO Mn CN Qa 2 RV40 AR PCOl s 3 a56 15 z C33 coi co4 C44 R44ty 3 wo s 2 q 2tiig 8 cog re ef 178 o ly KO i...

Page 354: ...s 5 6 _ 3 7 MSs e a L40 Pic2i Clim Ds ci3g 5V 2f Jas 5 F C42 Dil 2 3 _ OV C WV griae R 40 jo inten CN2 FDD2 CNS 7 N D4 RO2 if Y Vv LO cw 12V 7 ON bs 4 1 5V MAIN J Sw O R45 2RO3 R44 D46 ew 4 K cosw A C44 ae RF40 cno LA ike S515 ov N 2 u TH4O 4 C50 D Ro t t Oz R42 CN 4 PCBY 250 VAC Lis ov TSA R43 1C33 c80 pt IC32 R37 2 2 ARI 1 5V SW LL 12V Oo gRS3 5 6 3 5 3 _ py c5IZ _ Lo o R80 R 8 ahs PCBX CI 5V E ...

Page 355: ...R107 R105 R106 R104 R115 R108 R112 R113 R109 2103 R110 S R116 R11 Y TH101 R102 Sao C101 D101 3 2 4 O b b Figure 7 4 PSU Circuit Drawing II V 21 ...

Page 356: ......

Page 357: ...ORDER NO DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit ll Plasma Display Unit IV Keyboard V Power Supply Unit VI Floppy Disk Drive VII Option e i Panasonic _ Matsushita ...

Page 358: ......

Page 359: ...JU 58X JU 581 L JU 59X JU 591 JU 465 JU 475 2 2 3 5 inch FDD 67 5TPI _ JU 31X_ y 312 JU 313 JU 314 L_____ 435TP _ _ JU 32x JU 322 JU 323 JU 324 L_ JU 36X JU 362 JU 363 JU 364 3 SPECIAL TOOLS The following special tools are used for FDD maintenance TABLE3 1 Part No Tool 5 25 inch 96TPl Quantity 3 5 1nch JA 56x JU465 JB 58x 59x JU 475 Exerciser K K K 1 Alignmentdiskette 817 560 817 581 JU O1AA 1 2 D...

Page 360: ...rong operating procedure wrong programming or use of a defective diskette or soft errors due to external causes such as contaminated air and random electrical noise are often attributed to a drive failure or maladjustment Unless a visual inspection of the drive reveals an evident assembly fault or a defect always confirm errors with another good diskette and another known gooddrive Soft Error Dete...

Page 361: ...ack number on which the headis located and move the head away from it And read it again Compatibility Error The data which is written by one drive may not be read by another This error is called a compatibility error which can be caused mostly by the following The check points are also mentioned below 1 Head misalignment Refer to Adjustments and Confirmation Item 9 5 2 Head output too low Refer to...

Page 362: ...W ON amp NO Check item 1 Flashes Table 6 1 YES lane NO Check Item 2 Lights Tabie6 1 YES RECAL SW ON Track O LampLights at Table61 3 Track 0 Head Road Operation OK Check tem 4 Table 6 1 YES y Set Address SW to Track Seek Operation OK Write SW ON Check Item 5 Table 6 1 Write Waveform on Oscilloscope OK Check Item 6 Table 6 1 Write SW OFF Read Waveform on Oscilloscope OK NO OK after NO head cleaning ...

Page 363: ...uide shaft contamination or damaged wm a 3 PCB stepperdriver circuit Alep soe Be 6 No WRITE 1 See Item 1 2 See Item 4 3 Head disconnected we og 4 Head shorted a wg 5 HDL bail height wrong 6 PCBwritecircuit Repair Kk hoe 7 No READ 1 See Item 1 2 See Item 4 3 See Item 6 4 PCB read circuit a 8 READ ERROR 1 See Item 1 2 See Item 4 3 See Item 7 4 Alignment a a 5 Azimuth fo ee a 6 Burst Unadjustable Una...

Page 364: ...ate 1 Recalibrate and return to and return to and return to 8 Asymmetry 39 600ns 79 600ns 76 350 ns 9 Head load time 50 ms JU 591 595 475 JU 455 465 item Parameter TRK VALUE TRK Value 1 Index period 32 166 7 Jt 16 32 200 0 2 ms ms High 200 High 0 2 ms Low 2 Outputlevel 76 120 mV or 39 79 140 120 mV more or more 3 Radial Alignment 32 70 16 32 70 4 AZIMUTH 68 18 34 68 18 5 Index burst 68 200 34 68 2...

Page 365: ...a with write protect hole open hole closed 9 3 Head Output Verification Use a new diskette if possible to identify head failure for this check 1 Insert a good diskette 2 Run the motor 3 Step to the track specified in the output level column of Table 8 1 4 Connect the oscilloscope probe as specified below CH1 CH2 EXT 25 inch TP1 TP2 TP7 IX INDEX 3 5 inch 71 T2 Invert channel 2 and select the Add mo...

Page 366: ... 1 1 Insert an alignmentdiskette CAUTION Be sure to leave the alignment diskette under room conditions for 20 minutes before adjustment 2 Step to the track specified in the Radial alignment column of Table8 1 3 Leave the oscilloscope in the same condition as mentioned in section 9 3 4 Check the output waveformsfor sides 0 and 1 They should appearas in Fig 9 2 5 The two waveforms should appear in t...

Page 367: ...100 The lobe ratio calculated by the above formulas should meet the specifications on item 3 of Table 8 1 If the above requirement is not met loosen the two mounting screws for the stepper motor adjust Seek from track 0 to track 40 and from track 79 to track 40 and confirm that the adjustment has been completed After the radial adjustment be sure to confirm track 00 sensor adjustment 9 8 and headc...

Page 368: ... inch A 12 DAD 15 Fig 9 4 Azimuth Waveforms 9 7 Index Burst Verification 1 Insert an alignment diskette Seek to the track specified in the B column of Table 8 1 2 Set the oscilloscope time base as follows 6 25 inch 50 us division 3 5 inch 1 ms division 3 Check that the time from oscilloscope start to the first data pulse meets the I B specifications of Table 8 1 DAD system 4 If the specifications ...

Page 369: ...urnsto track 00 c If the carriage does not return to track 00 in Step b or if it contacts the limiter of the stepper motor the stepper motor assembly must be replaced because adjustmentis useless 9 10 Limiter Adjustment 3 5 inch 1 2 3 4 5 Seek to track 0 Write 2F data on track 0 and measurereadlevel Loosen the limiter mounting screw to free the limiter Move the limiter until it just touches the he...

Page 370: ...eeeel Fig 9 7 Asymmetry Waveform 10 PANASONIC ALIGNMENT DISKETTE Table 10 1 Cs SE ONES EER RAP OING ALS 96 817 560 1U 465 68TRK 68RTRK 32TRK JU 475 96 817 581 JU 58X 61TRK 61TRK 36TRK 100 817 570 JU 570 Table 10 2 3 5 inch Alignment Diskette TPI P N Index MODEL Burst Azimuth Radial 20 20 20 67 5 JU O1AA JU 31X 40 40 40 JU 32X 135 JU O1AA sU 36 WU 12 ...

Page 371: ... on the J3 connectoris facing upwards and J6 connectorpin No matches the P C B side pin No 11 2 Front Plate Removaland Installation See Fig 11 2 1 2 3 4 Operate the lock cam of the clamp assembly and turn theclamp handle in the direction of clamping Removethe clamp handle Remove the twofront plate mounting screws and take off the front plate Reverse the above procedure to reinstall Clamp Handle Lo...

Page 372: ...t a Temporarily fasten the Cartridge Guide Assembly b Insert a diskette or dummydiskette and clampit c Clamp repeatedly a few times to find a goodfit betweenthe collet and the inside diameter of the DD motor d Bind the screw of the Cartridge Guide e Check step c again if not good repeat steps a through d until the correct center adjustmentis achieved Fig 11 4 Collet Assembly Removal wu 14 11 5 Cla...

Page 373: ... Index Detector Index Detector Assembly Assembly Removal 11 7 Cartridge Guide Assembly Removal and W 15 1 2 3 4 5 6 7 nstallation See Fig 11 7 Removethe printed circuit board as described in 1 4 Removethe front plate as described in 11 2 Removethe shield plate mounting screw and take the shield plate off Removethe write protect sensor as described in 11 6 It is not necessary to remove the index de...

Page 374: ...tor Fig 11 8 Stepper Motor Assembly Removal 11 9 Carriage Arm Assembly Removal and VU 16 Installation See Fig 11 9 Remove the printed circuit board as described in 11 1 Removethe insulating paper and shield plate Removethe track 00 assembly as described in 11 3 Remove the stepper motor assembly as described in 11 8 Removethe two guide rod clamp mounting Screws Removethe carriage arm assembly guide...

Page 375: ... Reverse the above procedureto reinstall Whenreinstalling make sure that the drive motor connector Is connected in the correct direction 10 After reinstallation perform motor speed adjustment as described in 9 1 and also the adjustments necessary upon reinstallation of the cartridge guide as described in 11 7 Drive Motor Fig 11 10 Drive Motor Removal U 17 11 11 1 2 3 4 LED Assembly Removaland Inst...

Page 376: ...12 TEST POINTS Printed Circuit Board Top view GND INT TRKoe STEP TP5 TP8 TP12 x GND e ff TP2 TP1 TP6 Vout Vout READ DATA V 18 ...

Page 377: ......

Page 378: ...01901B4 Lift Spring 1 19 333D46817500 Pat 1 20 YTUFS56CLT2AN Collet Assembly 1 21 UF45CP3CAE1 Clamp Assembly 1 22 YJF4F00341B2 Clamp Bearing 1 23 YTF4H01720B3 Clamp Cam Assembly 1 24 333D36817692 Lock Cam 1 25 333D46624770 Lock Spring 1 26 YTUF45WP4AAA Write Protect Assembly 1 27 YTUF45LED LED Assembly 1 28 YTUF55SM Stepper Motor Assembly 1 29 YTF1G00500B4 Cord Clamp 1 30 YTF1E00300B4 Washer Head ...

Page 379: ... 2 CN YTFFC2LBW1B Connector 1 R28 FRA00040B478 Chip Resistor 1 CN8 FICO0180B400 Connector 1 R29 FRAQO040B468_ Chip Resistor 1 IR1 EXBRB7151JW Block Resistor 1 C6 7 24 FCCO0060B408 Chip Capacitor 3 IR2 EXBP84472J Block Resistor 1 8 9 FCC00040B420 Chip Capacitor 2 IR4 EXBL85368 Block Resistor 1 C10 11 IR6 EXBG88359S Block Resistor 1 Ser16 FCCOOO20B401 Chip Capacitor L FNCO0030B426 Low Frequency Coil...

Page 380: ......

Page 381: ...HEAD LOAD HLDA HL 1 PTN H WRITE GATE FQLO008 DMACT STEP INDEX DIRECTION TRACK 00 SIDE SELECT WRITE PROTECT INDEX PC IDX RD 150 3H2 psw WP PC WP WP Lv DRTN TKOO PC TRKZERO vc READY INDEX PE WP PE TKOO PE NOTE 1 NOT USED R26 12V ey 8_ 12W1GV 5V _ F 5 INDEX LA L _w ___ 7 3_ Tk Wi TKOO LA sg7 8_12VRTN ran v BEADFILTER L 5V DC eS 5V TP10 2 tpF 25v_ R8 cnn 3a IQR 2 C6 GND oneShF cy 12v0c sy4 L1 0 0ip BE...

Page 382: ...irere 2 Oso oa a 5_S__3a Lh a 2 1c3 4 FaLooos 178 x TP S70 T f RY i c ce 4 1 ComponentSide Top to 1 i t CGP w v _ 3H C Solder Side Bottom wa e fe 4 wo one m4 21 Ww N a aie R25 IT RS R2 9 Re o C2 5 is Tt9 FI 3 Leu e290 i ety C2 0 5 dd ai le 6G 2d He eS 7 s oS I 6 Fe ...

Page 383: ...k 00 Motor interrpter D D Motor Door Switch Option Head Load Solenold E Core R W Core Head Side 0 F D D Control Circuit Head Side 1 R W Core E Core FLEX To Host System Power Supply To Host System Signal 18 BLOCK DIAGRAM ...

Page 384: ... is menu driven and the main menu provides access to the various maintenance routines as shown below 2 1 HEAD OUTPUT ALIGNMENT CALIBRATION 2 2 TRACK OO SIGNAL CALIBRATION 2 3 CARRIAGE LIMIT CALIBRATION 2 4 INDEX TIMING CALIBRATION 2 5 AZIMUTH AND CAT S EYE PATTERN CALIBRATION 2 6 HEAD CLEANING 2 MAINTENANCE DISK DRIVE ASSIGNMENT 2 8 Reserved 2 9 EXIT 2 8 MENU SELECTIONS 8 AND 9 ...

Page 385: ...ich is used to perform the head cleaning procedure Insert the program diskette wait for the DOS prompt and start up the pro gram as follows A FDDMAINT ENTER When the program is loaded the screen will display the following menu show ing the maintenance routines MAINTENANCE MENU 1 HEAD OUTPUT ALIGNMENT CALIBRATION 2 TRACK OO SIGNAL CALIBRATION 3 CARRIAGE LIMIT CALIBRATION 4 INDEX TIMING CALIBRATION ...

Page 386: ...diskette in drive x Press any key when ready or press ESC key to return to the maintenance menu If you wish to abort the routine and return to the maintenance menu press the Escape key Otherwise insert the scratch diskette in the drive in dicated and press any key The next prompt will be Are you sure Y N Type Y to continue If you type N you will be returned to the first message for this routine Th...

Page 387: ... Press any key when ready or press ESC key to return to the maintenance menu If you wish to abort the routine and return to the maintenance menu press the Escape key Otherwise insert the alignment diskette in the drive indi cated and press any key The screen will display HEAD continues to seek TRACK OO and TRACK OL Check TRACK OO signal Press any key to return to the maintenance menu The read writ...

Page 388: ...ted The screen will display the following sub menu 1 HEAD position at TRACK OO Carriage 2 HEAD position at TRACK 39 Carriage 3 EXIT SELECT MENU __ Limit check limit check 1 to move the head to TRACK OO The following display will appear HEAD position TRACK OO Check carriage limit Press any key to return to the sub menu Press any key to stop the routine and return Enter 2 to move the head to TRACK 3...

Page 389: ... routine insert the alignment diskette in the drive indicated and press any key The screen will display the following sub menu 1 HEAD position at TRACK O1 Index signal check 2 HEAD position at TRACK 34 Index signal check 3 EXIT SELECT MENU __ Enter 1 or 2 to move the head to TRACK O1 or TRACK 34 respectively The following display will appear HEAD position TRACK xx Continuing READ operation Check I...

Page 390: ...ll display the following sub menu 1 AZIMUTH pattern check HEAD moves from TRACK OO to TRACK 34 2 CAT S EYE pattern check HEAD moves from TRACK O00 to TRACK 16 3 CAT S EYE pattern check HEAD moves from TRACK 34 to TRACK 16 4 EXIT SELECT MENU __ Enter 1 to run the azimuth pattern check Enter 2 or 3 to run the cat s eye pattern checks The following display will appear HEAD position TRACK xx Continuin...

Page 391: ...ning the disk heads To run it enter 6 from the maintenance menu The following display will appear 6 HEAD CLEANING Insert cleaning diskette in drive x Press any key when ready or press ESC key to return to the maintenance menu To run the routine insert the head cleaning diskette in the drive indicated and press any key The screen will display the following HEAD continuing SEEK operation between TRA...

Page 392: ...SK DRIVE ASSIGNMENT Current drive assignment is x Assign disk drive A or B Enter the desired disk drive assignment When the program is started up the default drive is B After you have entered the disk drive assignment A or B the program will return to the maintenance menu Menu Selections 8 and 9 Menu selection 8 from the maintenance menu is reserved for future expansion Menu selection 9 is the EXI...

Page 393: ......

Page 394: ...DER NO DATA 85012 TechnicalGuide Portable Computer JB 3300 General ll Logic Unit Il Plasma Display Unit IV Keyboard V Power Supply Unit VI Floppy Disk Drive Vil Option e Panasonic MateusElectsTradingCo Lt ...

Page 395: ......

Page 396: ... and other additional items Specifications Host interface Conforms to IBM personal computer No of connectable devices 1 or 2 magnetic disk drives with ST506 or equivalent interface Sector length 512 bytes per sector Data error correction function Errors in ll bit bursts correctable by 32 bit error correction code ECC Correlation Table for Connected Magnetic Disk Drives Under the fixed disk BIOS pr...

Page 397: ...0 1 320 4 128 320 7 0 0 0 306 4 0 306 SW1 O OFF 1 ON P C Starting write precompensation cylinder W C Starting reduced write current cylinder OFF Normal operating condition ON One disk drive is connected as drive 0 and its disk storage space is divided in half one half of which is treated as drive O storage space and the other half as drive 1 storage Space simulation of two disk drives VII 2 ...

Page 398: ...data from the host computer into MFM data and executes read and write operations vis a vis the disk drive 3 NDC 841 This LSI converts signals between the controller and the NDC 843 LSI for the IBM I O channel 4 NDC 840 This LSI operates in the HDC according to commands sent from the MPU Z80 It converts 8 bit parallel data sent by the host computer into serial data and also converts serial data sen...

Page 399: ... slot dimensions of the IBM XT to enable easy mounting Power Supply Required voltage DC 5V 5 Required current 1 1 A typical 1 4 A maximum Connectors CNL This connector is used by the drive control signal 33 31 2927 3 CN1 Connector 0000 oo Pin No OoOdgd0 Oo t 34 32 30 28 4 2 VII 4 ...

Page 400: ...11 Write Fault 14 13 Head Select 2 16 15 Reserved 18 17 Head Select 2 20 19 Index 22 21 Ready 24 23 Step 20 25 Drive Select l 28 27 Drive Select 2 30 29 Reserved 32 31 Reserved 34 33 Direction in Note The JP6 setting can be used to change signal to Head Select 2 The setting method is described in section 3 2 below VII 5 ...

Page 401: ...s J 19 17 18 3 W CN2 Connector OO O DO Pin No 00 oO O0QO x 4 20 18 4 2 Signal Pin Ground Pin Signal Name 1 2 Drive Selected 3 4 Reserved 5 6 Spare 7 8 Reserved 9 11 Spare 10 12 Spare 13 15 MFM Write Data 14 16 MFM Write Data 17 19 MFM Read Data 18 20 MFM Read Data VII 6 ...

Page 402: ...A 13 Address Bus Al A 30 AO A 31 D 7 A 2 D 6 A 3 Data Bus Di A 8 D O AQ TOR B 14 1 O Read TOW B 13 I O Write AEN A ll Address Enable RESET DRV B 2 Reset Drive TRQ5 B 23 Interrupt Request 5 DRQ 3 B 16 DMA Request 3 DACK3 B 15 DMA Acknowledge 3 5 V B 3 5 V Power 5 V B 29 GND Bl GND B 10 GND GND B 31 VII 7 ...

Page 403: ...cuit this to enable use of the memory The address setting is short circuit O and open circuit l Address settings Al3 to Al9 are wired on the PCB to C8000Hex JP2 Controller base address setting JP 2 O 6 0O0O0000 0 OO00000 as as az7 ag A4 A6 A8 The address setting corresponds to short circuit O and open circuit Ll Address settings A3 to A9Y are wired on the PCB to 320 Hex JP6 Magnetic disk drive con...

Page 404: ... with the IBM PC XT s bus timing To write commands or data from the host computer the commands or data are first set in the NDC 843 s internal register and then are transferred to RAM by the NDC 840 s DMA mode Similarly to read status data or other data the data are first read from RAM and set in the NDC 841 s internal register and then are read into the host computer Time Chart of Principal Opera...

Page 405: ... ACK signal fF é B D0 to 7 xX Defined Command Byte x DATA O to 7 xo X c p REQ no TOW I Y Data write program mode 320H Output SS ee oeaN baccarat j A request signal is received when the I O and C D signals each reach the L level When the data byte has been prepared to send to the controller in response to this send an ACK signal DO to 7 x Defined Data Byte x DATA O to 7 Output I O ype TOW ay aa VII...

Page 406: ...et data bit O to 1 and record it on the mask register then when a request signal is received send a DRQ to begin DMA mode operation DO to 7 x Defined Data Byte xX DATA 0 to 7 x Output T O C D s DACK3 NS 1 Tow LO _ DRQ Yo VII ll ...

Page 407: ... is received when the I O and C D signals each reach the L and H levels When the host computer has received the data byte in response to this send an ACK signal DO to 7 out SX _séDefiined Data Byte xX DATA O to 7 T O __X C D x a J ON _ DRD VII 12 ...

Page 408: ...nd a DRQ to begin DMA mode operation DO to 7 Cutpuy Defined Data Byte DATA O to 7 _X Y xX T O C D REQ DACK3 TOR ACK DRO DRD g Status read control signal 321H Set the AQ and Al signals to the H and L levels and read them so that the control signals REQ I O C D BUSY DRQ and IRQ are read DO to 7 SB Al a AO Ne IOR VII 13 ...

Page 409: ...D to the H level and reads the status The controller sends an ACK signal when the host computer has received the status byte DO to 7 Defined Status Byte x DATA 0 to 7 T O C D _ REQ X __xX AO 1 IOR oY IRQ i oY 1 Switch read The DIP switch status is read to DO to 7 DO to 7 ss Output _ TOR Fe fo SW1 to 8 Fixed VII 14 ...

Page 410: ...IOW signal is received when AO and Al each reach the H and J levels DATA 0 to 7 Al AO ated weed TOW RST IRQ DRO ST TS persue etna ewe ed High Impedance TP eb High Impedance VII 15 ween Flee ees ee ae ene omen wee ...

Page 411: ...e chip RAM is used the maximum sector length is 512 bytes Bach buffer perform data transmission using the time division mode b Transmission speed for host computer and buffer When transmitting data between the host and the 5 inch flexible disk drive the data is temporarily stored in the buffer register to enable a freely selectable transmission speed However the sector interleave is determined by ...

Page 412: ...ission speed o The load for the host side hardware is light o Cycle stealing and high priority processing is possible for the host side an o Processing efficiency does not decrease when the multisector mode is used Example Read data from disk to host Disk drive transmission speed 5M bit s 1 6 us byte Host computer transmission speed 3 2 us byte SECTOR 4 SECTOR epreave SECTOR 2 SECTOR 3 SECTOR SECT...

Page 413: ...co CoO Ci C2 C3 C4 C5 C6 C7 CO Cl buffer and host C2 C3 C4 C5 C6 C7 CLK HoHe HRQ__Y Tutcl I TCMR HLDA THLP EY PHASE 0 _ ones fee eee ade eee ome ee eet e eee ames ame oe ewe eee ees eee ee hee oe oe oe ge eed ene feu aijene qeme come come Bem oemee amg came eee gee eee ome eee oe p ame ome fee ee eee cee cee eee cme eee Gee ee cee eee aie ee wee eee ome DIR reas ADR STB TCAR ADR 0 7 My x TCAE My T...

Page 414: ... co co co co ct c2 c3 c4a cs ce c7 co Cl C2 C3 C4 C5 C6 C7 CLK tL FTCHO l HRQ fi THLE t i HLDA _ PHASEOIH ITCMR ADR STB S N TCAR t j ADRO 7 yA Xx Teak 11 ADRE TCMRH _ M READ f TCMw jTCMRH M WRITE toas ymrp ITMRDH xX TWDA2 So Li TDAW2t l DIR VII 19 ...

Page 415: ...s Power on or Reset Initialization Hardware Memory Host Check of Controller Selection No Select Yes Command Request to Host Parameter Setting of Specified Logical Unit Command Control Format Write Seek Read Other send Completion status VII 20 ...

Page 416: ...nit Address Erase Specified Track Write ID for ID Table Cylinder 001 head 02 interleave 5 Specified Track Cylinder Head Sector 0100 02 00 0100 Q2 Q7 0100 02 OE 0100 02 04 0100 02 OB Write Data Buffer 0100 02 OL Contents to Speci 0100 02 02 fied Track Sectors 0100 02 OF 0100 02 05 0100 02 OC 0100 02 02 0100 O02 O09 0100 O02 LO QO100 Q2 06 1 0100 O02 OD 0100 O02 03 End 0100 02 OA VII 21 ...

Page 417: ...n The step pulse for the seek operation is produced by the FPU NDC 840 The host issues a command to set the step rate value _ nana DIRECTION IN t l i STEP l l typ 52ys I 30ms je S2ne pf some 3 2yus typ Aeeording to step rate VII 22 ...

Page 418: ...Cylind er Address Yes Current Address Higher 1 Step Pulse Value Current Value Specified Value Specified Address Highe Y Direction Out Reverse Step Pulse Value Specified Value Current Value Direction in Forward 1 Step Output Timer 18 us to 3 ms Step Pulse Value l VII 23 ...

Page 419: ...storage are first divided by the VFO LSi NDC 842 into NRZ data and clock data and then are sent to the NDC 840 serial parallel convertor error correction code The data converted from serial to 8 bit parallel by the NDC 840 are sent to RAM by the NDC 840 s DMA mode The NDC 840 executes error detection of read data and if there are 11 bits or less of successive errors it and the CPU 2 80 correct the...

Page 420: ...1 Track Completed Sector Address 0 Head Address 1 1 Cylinder Completed Yes Seek 1 Step Head Address 0 Cylinder Address l Yes 4 Command Not in Controller Error Seek Error 15 H Error ECC Error in ID Field 10 8 ECC Error in Data Field 11 H AM not Detected 12 H Sector not Detected 14 H ECC Error Processing 8 H Bad Truck Read 19 H Send Read Data to Host Send Read Data to Host and Read Data From Disk VI...

Page 421: ...write data is sent from the host to RAM and from RAM to the NDC 840 where it is converted into serial data Then while the ECC error correc tion code generator generates the ECC the data are sent to the MFM genera tor NDC 842 for conversion into an MFM pattern Finally the data are sent to the disk The ECC is tagged onto the end of the data and also sent to the disk VII 26 ...

Page 422: ...ek Specified Unit Address Check Track Address Read ID Send First Write Data from Host Block Count 1 No Write Data to Disk and Send Write Data From Host Sector Address 1 1 Track ompleted Yes Sector Address 0 Head Address 1 1 Cylinder Completed Seek 1 Step Head Address 0 Cylinder Address 1 Yes Illegal Command Write Data to Disk ...

Page 423: ... by the REZERO command During the power on operation the controller cannot transmit the DRDY signal until this Signal has been detected This signal indicates abnormal condition in the disk drive Read write cannot be executed when this signal is low This is a pulse output once per disk revolu tion to indicate data track opening This signal indicates that the disk drive is operating normally Seek re...

Page 424: ...e DATA It is sent as a differential signal b MFM READ CONT This data signal is read from the drive DATA It is sent as a differential signal INDEX L SECTOR OI LAST SECTOR SECTOR 00 j oO to TRUCK GAP 4 GAP 1 ISYNC 1D JGAP2 DATA GAPS SYNC 1D GAP2 DATA GAP 4 FORMAT 16 byte 3byte lObyte ISbyte FIELD az p3bte ObyteliSbyte FIELD _ SELECTABLE FORMAT OPERATION DRIVE us MIN HEAD SEL us MIN WRITEGATE WRITE O...

Page 425: ...Sv suitable part loo0n SN74LS14N or other 3 suitable part l ys 7 73300 l m max I Flat cable or twisted pair cable impedance 1008 10 b Data signals The driver receiver configuration for the CN2 connector s MFM READ WRITE DATA signal is shown below Sending Side Receiving Side AM26LS32 or other Suitable part AM26LS31 or other Suitable part cee ts ee ee ee S100 t t t t 777 7 _ 6m max _ _ Flat cable or...

Page 426: ...ECTION IN XY Ye _ _ 40s typ _1 300ys typ STEP i oms typ or rm TT l4pis typ SEEK COMPLETE Ops MIN b Seek operation buffer mode seek Oys MIN 300ups _ Las ps typ READ GATE DRIVE SELECT 7 aa SRECTION eo typ Step t _ 40pstyp _ 300ps typ SEEK COMPLETE os Hh 4us typ ops SHE MN __ MIN _ 300ps typ GATE VII 31 ...

Page 427: ...e comparator are built in c MFM and FM recording method and response d Missing data pattern detection function e MFM write compensation support f 5 VDC single power supply Operation of NDC 842 a Reset input 1 RST RESET Clear all registers including the high active register and initia lize the NDC 842 chip b Clock input 1 4FC 4F CLOCK This clock is used for internal control and for the write circui...

Page 428: ...re used to input the receiver output for the data sent from the disk drive The DSI signal 1s used to select between the RR1 and R2 Signal Their correlation is shown below DSL RR1 RR2 Low level Selects RRL High level Selects RR2 The leading edges of RR1 and RR2 are based on risen pulses This is set by the disk drive control signals RGT READ GATE This control signal is a HIGH ACTIVE gate signal for ...

Page 429: ...DATA bit counter Consequently when the SYNC field is set as 00 a control signal that is at low level during detection of IF cycle patterns in MFM mode or 2F cycle patterns in FM mode DDO DD1 DD2 DELAY DATA O 1 2 All of the leading edges are risen pulses Although the raw data selected by the DS1 signal is fundamentally output as DDO as long as there is no DDI input the DDO can be a high level signa...

Page 430: ...d to write operations 1 2 WDN and WMD WRITE DATA NRZ WRITE MODIFIED DATA When serial NRZ data synchronized to the 2F clock is input to WDN from the HDC or FDC the data modified by MFM or FM is output as WMD PED PND and PLD PRECOMPENSATION EARLY NORMAL LATE DATA In MFM mode only precompensation selections EXT and YES are effective The amount of compensation varies according to the type of disk driv...

Page 431: ...t Pattern Precompensation Data O Q000 0 NORMAL CLOCK 1 ooo1 EARY CLOCK 2 0010 _ NORMAL DATA 3 Oo0l1l LATE DATA 4 O10 0 _ _ 5 O1l01 _ 6 O11 0 EARY DATA 7 Ol1ltl1l1 NORMAL DATA 8 1000 LATE CLOCK 9 Lool NORMAL CLOCK A 1010 NORMAL DATA B 1011 LATE DATA Cs 1100 These data are effective during D lilol MFM mode i 1110 EFARY DATA F lT1lill NORMAL DATA When internal precompensation is selected 10 ns 30 of ...

Page 432: ...7 4 Timing ae Input of mode setting I DB DBO Y 7 O KL OUT MIN 3 8n L Effective Data raren _ MHOLD ee i MIN 6 8ns To 3 MIN ns Vit 37 ...

Page 433: ... and 2F clock output I4Fo 060UVY O 2FC typ _J 5ns typ_ i7ns Cc Read input and output 1 Read clock and NRZ output data VII 38 PCR FO _ la b Bit Sel f ic Ll RDT Logic typ TYP _J 3ns 8 Ins y AMF aa typ typ 6 6ns f 6ns 6ns ...

Page 434: ... YP typ 24 3ns 19 2ns yp ce aA RCK Non Read IFN _ _typ typ 6 3ns l 2 ns 3 iVCK and read strobe i1RSE iRSN and iRSL IVCK IF Eo e7 0 Data Separator Window Internal I I IRSE IRSN Data Separator Clock Internal typ 10 7ns st typ I2 6ns Window Window IRSL 7 mi ta typ 8 6ns VII 39 ...

Page 435: ... Min 8ns Min 4ns poe 2 MFM data WMD WMD Data Bit LJ PL typ 1 72ns Clock Bit typ 72ns ODWD Output SPOT TS Ta Precompensation Mode INT Write Precompensa tion Data EARLY Data _ sn 9 MAX 13ns NORMAL Data Min 7ns 31 5ns MAX 13ns _fVL LATE Data Clock bit is the same for EARLY NORMAL and LATE data VII 40 ...

Page 436: ...ODWD output we eeeeeeee e Precompensation mode EXT IPED __ IPND IPLD typ Il 2ns ODWD J VII 41 ...

Page 437: ...8 LSI SPECIFICATION 8 1 NDC 840 a Pin assign VII 42 ...

Page 438: ...s o pprr 28 t rrxo 4s o tac2 68 o aog 9 oO DRO 29 I SELD 49 O TAG3 69 O Ads 10 o apreE 30 o ptr 50 o TacG4 70 o ao7 11 I CLKO 31 1 0 STEP 51 I RD 71 O A06 12 vss 32 I RC 52 vss 72 I ics 13 I CLK1 33 vpp 53 O WD 73 VDD 14 Oo PHAS 34 I svc 54 1 o pDB7 74 I REST 15 O IMO 35 o mstp 55 I o DB6 75 O A05 16 O REFT 36 o Rwc 56 1 o DB5 76 Oo aA04 17 O CHOE 37 Oo HDS1 57 1I o DB4 77 O AO3 18 O AMEO 38 O HDS...

Page 439: ...vnenteirssenaamn enennecmnremnanenaeemmetie eee praeneereeeeereannaernenenaeeensocsat ponerse eae een READ DATA READ D WR ITE DATA WRITE D READ CLK READ C AM ENABLE O B STBO AM ENABLE B STB 1 INDEX INDEX READY READY WRITE FAULT SEEK COMPLETE TRACK OO DRIVE SELECTED FAULT SEEK END ON CYL SELECTED DIRECTION ECC WRITE STEP SEEK ER MICRO STEP B9 REDUCE WC B8 HEAD SEL 2 BO HEAD SEL 2 B1 HEAD SEL 2 B2 H...

Page 440: ...26 I O D1 38 I D REQ 3 I O DBL 15 I EVEN ODD 27 T O DO 39 I TIM OUT 4 t O DBO 16 I ACK 28 I HI CLOCK 40 O LO READ 5 I 2FCLK 17 T SEL 29 I TEST Al O 10 WRITE 6 GND 18 I RESET 30 O RESET3 42 O IFCLK 7 T AFCLK 19 VCC 31 GND 43 VCC _____ DATA 8 O BUSY 20 T O D7 32 I RESET2 44 I O PARITY 9 O MSG 21 I 0O D6 33 I INPUT 45 1 0 DB7 10 O REQ 22 T O D5 34 I OUTPUT 46 I O DB6 11 t O 23 T o D4 35 I CS A7 I O D...

Page 441: ...8 BIT TA BUS PARITY END DO 7 PARITY BIT pBO r BUSY STATUS MSG ary TNEUT 110 INPUT CID OUTPUT CS SEL SEL ADR 110 READ 10 READ 110 WRITE DIR REQ CHOEXC TIM OUT _ ACR DATA REOQ HI CLOCK GFCLK RESET RESETS TEST RESET2 2FCLK VII 46 ...

Page 442: ...O fr a r O O Oo e O a Ay Ay A UO A A O O O mn 1 KH KH KH KH O O O O O c 4 ro N un LO CO OV Oo eH Ay re aa r ro rr re a N N r O a oO N x 2 4 r N a A A A QA nM wy aa os A A A A 4 AG m KH O O CH KH KH HK HH KH eH C 4 N st Te WO GO OY oO Ay aa oasals awn R ro s aao s da 3 _zo0 fh zaz yguols xn R ort mn oza a oasu 8 ovat s otor 8 on do 5 _a BE oono 8 an ono Fy soo NDC 842 Riba BloueH Blouwer aloavu RJO...

Page 443: ...b Block diagram 1 Condiguration NDC 842 CHIP READ OUTPUT READ INPUT IRGT READ GATE READ BLOCK IDB IDBO MODE IA OUTPUT IA O ICS lOUT WRITE INPUT WRITE OUTPUT WRITE BLOCK IWGT WRITE GATE VII 48 ...

Page 444: ...LAMP 4F CLOCK ORCK READ CkKOCK 2 FCLOCK CLAMP GEN SYNC IRDM DETECTOR IRR RAW DATA IRR2 SELECTOR IDS DRIVE SEL 1 IDD ODDO IDD2 OCGH OCGL ODCH ODCL IRSE DATA IRSN ORDT SEPARATOR IRSL READ DATA AE O O AMF AMW MISSING DETECTOR AM FOUND VII 49 ...

Page 445: ...K MFM FM OWMD GENERATOR IWON DELAIED DATA WRITE DATA GB a a wi zl yy YY PRECOMPE PED DATA PNO 1 DATA 5 TOR ODWD IPLD GENERATOR ELEC i a oO 2 ql wi PRecomPe Oo w q J PATURN Z DETECTOR MISSING CLOCK GENERATOR LAEO 1 AMW DEC MISSING Se VII 50 ...

Page 446: ... 48 m PHP vo WwW PpPH pu D OD A A T T V A A C 2 1 C OPH PU 36 35 34 33 32 31 30 ke 1H so NO oO p WO Q24 ran yO an N Cc wan men 29 28 27 26 25 FUJITSU MB111T131R1 NDC 843 4 5 6 7 8 A AIv it 1 2 0 C O R C W VII 51 9 1011 12 Ome ro QZ No oO 24 23 22 21 20 19 18 17 16 15 14 13 SA2 IRQ DRO Cs RESET DACK D7 D6 D5 D4 D3 ...

Page 447: ...LL lo Do BSOL 28 Sw2 LSW2 40 ACR OACK 5 A2 TA2L 17 D7 BSOO 29 SW1 LSW1 4 RST ORST 6 TOR LIOR 18 DACK TDA3 30 DATAO BSLS 42 SEL OSEL 7 Vcc 19 GND 31 Vcc 43 CND 8 TOW LIOW 20 RESET ODRQ 32 DATAL BS14 44 BUSY LBSY 9 DO BSO7 21 CcSs ODRQ 33 DATA2 BS13 45 REQ TREQ 10 D1 BS06 22 DRQ LRET 34 DATA3 BS12 46 I O LIOB LL NC 23 IRQ ICSB 35 NC 47 Cc D ICDB 12 D2 BSO5 24 SA2 ISA2 36 DATA4 BSL1 48 DRD ODRD ...

Page 448: ...b Block diagram TRI BUF D7 DATAT D6 DATA6 D5 DATAS D4 DATA4 D3 DATA3 D2 DATA2 DI DATAI DO DATAO SELECTOR SW SW2 SW3 SW4 BUSY C D 1 0 REQ ICRI ICW cS AO Al A2 SEL SAZ ACK IRQ DWT DRQ DRD RESET RST VII 53 ...

Page 449: ...7 NC 39 I STEP 4 O Vvcl 16 O MSTP 28 I vcl 40 I MSTP 5 O FL 7 O W GT 299 t ri Al I W GT 6 o Rwe 18 o HS 2 3 30 t RWe 42 zt HS 2 3 7 VCC 19 GND 31 VCC 43 GND 8 O HS 2 0 20 I D SEL 32 I HS 2 0 44 O D SEL 9 o Hs 2 1 21 I SKCMP 33 I HS 2 1 45 O SKCMP 10 O HS 2 2 22 I TRKOO 34 I HS 2 2 46 O TRKOO 11 NC 23 I W FLT 35 NC A7 O W FLT 12 O DS 1 24 I RDY 36 rt DS 1 48 oO RDY VII 54 ...

Page 450: ...INDEX TYP Note Pin Number VII 55 ...

Page 451: ...b Block diagram NDC 840 Control Signals SE Driver _ V Receiver Receiver froma at es 7 ST506 NDC Signals 0 T ____t e a Y Driver C 5 V Driver Interface ST506 or Equivalent VII 56 ...

Page 452: ... PARTS LOCATION ...

Page 453: ......

Page 454: ...10 CIRCUIT DRAWING Cea NOC 843 Cl O ipF DO o07 8 D ST READ 5 HRST 2 C2 OO pF Host Interface 1 NDC 843 VII 59 ...

Page 455: ...DATA H CLK TST 34 HDBPAY 45 46 47 OO OOO OO OOOO OO OOOO OOO NOC 841 csi pDiR G CHOExc ora TIME oOuTG TOREAD TOWRITE 3 4 F CLK 4FCLK 6 2FcLK RESETS tos lOpF 16V Host Interface II NDC 841 VII 61 ...

Page 456: ...ABLE O AM WRITE READ GATE WRITE GATE IOWR ITE COOQOE O 7B 26LS 31 a TAG4 lS 8 66900 i 2 35 ae REDUCED WRITE CURRENT HEAD SELECT 2 0 HEAD SELECT 2 1 CHOEXC HEAD SELECT 2 2 DRIVE SELECT SCETS DRIVE SELECT 2 neSeTS DIRECTION IN STEP WRITE GATE RM RM 2 SEEK COMPLETE TRACK OO WRITE FAULT READY INDEX GND GND GND GND GND GND Figure 6 3 HDC VII 63 ...

Page 457: ...LS32x4 Ls244 1 72 7 RM5 6 2KQ x 4 _ 2 IFCLK MREAD 6 MwWRITE G IOREAD 2 SF SF SF G INTRI 3 HRO IOWRITE LSOO x 3 GB HLDA 2 HREQ oO ho 8G 13 q 8G 8G paTao 7 36 ADR O I5 Oo RESET3 beRPrPPpPp b b PP Pb YP oO On Da bw yn b pb oO VI 65 ...

Page 458: ... yee ADRO I5 2 DATAO 7 M READ 4 M WRITE 8725 6264 RAM cS ae OE A 6C A2 DO A 3 DI A 4 D2 A 5 ATA D3 A 6 4 16 14 TAS 04 A 7 7 15 05 A8 TAG 16 D6 A9Q roo t 1 23 77 LL JP8 vec CS2 Vec po 07 B 13 ST READ 1 B 13 ...

Page 459: ...0 1pa1 IRSE wNc oaTao pATAC S21 1080 trsi ne r 3 MFMWDATA aori ADR 38 tray 1 14 MFMWDATA aAoRo ADRO 3711 a0 La r 17 MFMR DATA tsz 28dics o owo f DISK WRITE DATA 12 r MFMRDATA 2 iOWRITE 21d tout 7 8 2 4 GND Vee 2p242_ _ LS 6 8 3 WRITE DATA 28 1WON L _1 11 12 27 26LS 31 WRITE GATE IWGT 622 C23 WT 7B 15 16 Ay uF AM wRITE 26 TT AMW 19 20 GND 25 11 32 3 AM ENABLEQ IAEO GND 2 3 READ GATE 24 Ret rRsTPe a...

Page 460: ...TPG Oo suo my c32Z wy c30 L2 lOuH P47uF 150 pH c 4 Ls lOO wH Si wt 1 ene D3 5V 7 O 5v I ib i JP 9 S CNB B 6 4 7 14 3 29 5V C27 TL497 we aTuF R29 RSI 1 2KQ iO 777 2H 13 2 10 5 3 S R3O 3 9KQ 1T JC26 PF 1 10 31 GND 5V VII 71 ...

Page 461: ...each sequence of the trouble analysis of the NDC 5027 Magnetic Disk Controller 11 2 Configuration Host system IBM PC XT Disk i i I F Controller I 11 3 Analysis Method Power on or reset Command receiving function Controller reset from the host system Command execution C End VII 73 ...

Page 462: ...l is output from MPU Z 80 6E Pin 39 If the RD signal is not output o Check if the BUSRO signal from MPU 2 80 6E Pin 43 is on the LOW level o Check if the INT signal from MPU Z 80 6E Pin 34 is on the LOW level If the BUSRO signal is on the LOW level Oo NDC 840 LSI is faulty FPU DMA Oo NDC 841 LSI is faulty HOST I F o 74LS02 3D is faulty If the INT signal is on the LOW level o NDC 840 LSI is faulty ...

Page 463: ... MPU peripherals 74LS32 5F 74LS244 6F 74LS00 8G 74LS74 4C ROM 6C or RAM 7C is faulty DRO does not rise even after one byte of command has been sent NDC 840 4B Pin 1 is on the HIGH level o NDC 843 1B or NDC 841 1A is faulty NDC 840 4B Pin 1 is on the LOW level o NDC 840 4B is faulty oO Some of MPU peripheral ICs is faulty Does not start even after the command has been transferred NDC 840 4B Pin 1 i...

Page 464: ... 4H Pin 2 and Pin 13 are 5 V o TL 497 2H is faulty o TL497 peripheral circuit is faulty 2 Check if the output from NBC 847 4H Pin 8 is 0 5 v 2 0 V o NDC 847 4H is faulty 3 Check the READ data from the disk o NDC 842 7E is faulty Oo NDC 840 4B is faulty o NDC 846 4A is faulty Oo 74L8123 7G is faulty c Some times an error occurs after the start 1 Refer to b 1 2 74LS8123 7G Pin 12 o Confirm the LOW l...

Page 465: ... occurs after the start 1 Refer to 4 b for errors in the ID section 2 DATA WRITE errors o NDC 842 7E is faulty o NDC 840 4B is faulty o NDC 846 4A is faulty Oo 26LS31 7B is faulty c Some times an error occurs after the start 1 Refer to 4 c for errors in the ID section 2 DATA WRITE errors Oo Refer to 5 b VII 77 ...

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Page 468: ...Printed in Japan 8601 50 A S K 610403 A ty ae ee WS ...

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