IRF IRAUDAMP5 Manual Download

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IRAUDAMP5 REV 3.1

IRAUDAMP5

120W x 2 Channel Class D Audio Power Amplifier

Using the IRS2092S and IRF6645

Jun Honda, Manuel Rodríguez and Jorge Cerezo

Fig 1

CAUTION: International Rectifier suggests the following guidelines for
safe operation and handling of IRAUDAMP5 Demo Board;

•

Always wear safety glasses whenever operating Demo Board

•

Avoid personal contact with exposed metal surfaces when operating
Demo Board

•

Turn off Demo Board when placing or removing measurement probes

Summary of Contents for IRAUDAMP5

Page 1: ...uez and Jorge Cerezo Fig 1 CAUTION International Rectifier suggests the following guidelines for safe operation and handling of IRAUDAMP5 Demo Board Always wear safety glasses whenever operating Demo Board Avoid personal contact with exposed metal surfaces when operating Demo Board Turn off Demo Board when placing or removing measurement probes ...

Page 2: ...ion Features 12 17 Efficiency 17 18 Thermal Considerations 18 Click and Pop Noise Control 18 19 Startup and Shutdown Sequencing 19 21 PSRR 21 22 Bus Pumping 22 23 Input Output Signal and Volume Control 23 26 Self Oscillating PWM Modulator 27 Switches and Indicators 28 Frequency Lock Synchronization Feature 29 Schematics 32 36 Bill of Materials 37 40 Hardware 41 PCB specifications 42 Assembly Drawi...

Page 3: ... two channel design is scalable for power and the number of channels Applications AV receivers Home theater systems Mini component stereos Powered speakers Sub woofers Musical Instrument amplifiers Automotive after market amplifiers Features Output Power 120W x 2 channels Total Harmonic Distortion THD N 1 1 kHz Residual Noise 170μV IHF A weighted AES 17 filter Distortion 0 005 THD N 60W 4Ω Efficie...

Page 4: ...Idle Power Consumption 7W No input signal Channel Efficiency 96 Single channel driven 120W Class D stage Audio Performance Before Demodulator Class D Output Notes Conditions THD N 1W THD N 10W THD N 60W THD N 100W 0 009 0 003 0 003 0 008 0 01 0 004 0 005 0 010 1kHz Single channel driven Dynamic Range 101dB 101dB A weighted AES 17 filter Single channel operation Residual Noise 22Hz 20kHzAES17 170μV...

Page 5: ... Setup Typical Test Setup Fig 2 Connector Description CH1 IN J6 Analog input for CH1 CH2 IN J5 Analog input for CH2 POWER J7 Positive and negative supply B B CH1 OUT J3 Output for CH1 CH2 OUT J4 Output for CH2 EXT CLK J8 External clock sync DCP OUT J9 DC protection relay output Volume J6 J5 J3 J4 J7 R113 S3 S2 TP1 TP2 CH1 Output CH2 Output CH1 Input CH2 Input G Protection Normal S1 LED 35V 5A DC s...

Page 6: ... If necessary adjust the self oscillating switching frequency of AUDAMP5 to 400KHz 5kHz using potentiometer R29P For IRAUDAMP5 the self oscillating switching frequency is pre calibrated to 400 KHz To modify the AUDAMP5 frequency change the values of potentiometers R21 and R22 for CH1 and CH2 respectively 12 Quiescent current for the positive supply should be 70mA 10mA at 35V 13 Quiescent current f...

Page 7: ... 1 2 5 10 20 50 100 W Blue CH1 4 Ohm Red CH2 4 Ohm Figure 18 Total Harmonics Distortion Noise THD N versus power output Fig 3 10 4 9 8 7 6 5 4 3 2 1 0 1 2 3 d B r A 20 50 100 200 500 1k 2k 5k 10k 20k 50k Hz 200k 100k Frequency Response Red CH1 4 Ohm 2V Output Blue CH1 8 Ohm 2V Output Frequency Characteristics vs Load Impedance Fig 4 ...

Page 8: ... 1k 2k 5k 10k Hz Pink CH1 1W Output Blue CH1 10W Output Cyan CH1 50W Output Green CH1 100W Output THD N Ratio vs Frequency Fig 5 Frequency Spectrum 110 0 100 90 80 70 60 50 40 30 20 10 d B V 10 20k 20 50 100 200 500 1k 2k 5k 10k Hz Red CH1 1V 1kHz Self Oscillator 400kHz Blue CH2 1V 1kHz Self Oscillator 400kHz Fig 6 Frequency Spectrum ...

Page 9: ...0 500 1k 2k 5k 10k Hz Red CH1 ACD No signal Self Oscillator 400kHz Blue CH2 ACD No signal Self Oscillator 400kHz Fig 7 Residual Noise ACD Channel Separation 120 0 110 100 90 80 70 60 50 40 30 20 10 d B 20 20k 50 100 200 500 1k 2k 5k 10k Hz Red CH1 CH2 60W Blue CH2 CH1 60W Fig 8 Channel Separation vs Frequency ...

Page 10: ... immunize the rectangular waveform from possible narrow noise spikes that may be created by parasitic impedances on the power output stage The IRS2092S input integrator then processes the signal from the summing node to create the required triangle wave amplitude at the COMP output The triangle wave then is converted to Pulse Width Modulation or PWM signals that are internally level shifted Down a...

Page 11: ... Filter L1 DirectFet C18 R32 B IRF6645 Q4 IRF6645 Q3 Simplified Block Diagram of IRAUDAMP5 Class D Amplifier Fig 10 System overview IRS2092S Gate Driver IC The IRAUDAMP5 uses the IRS2092S a high voltage up to 200V high speed power MOSFET PWM generator and gate driver with internal dead time and protection functions specifically designed for Class D audio amplifier applications These functions incl...

Page 12: ...gates the need for a precise reference voltage and sets threshold voltages for each of the four programmable settings Shown in the table below are component values for programmable dead times between 15 and 45 ns To avoid drift from the input bias current of the DT pin a bias current of greater than 0 5mA is suggested for the external resistor divider circuit Resistors with up to 5 tolerance can b...

Page 13: ...hed by the manner in which a fault condition is treated Internal faults are only relevant to the particular channel while external faults affect the whole board For internal faults only the offending channel is stopped The channel will hiccup until the fault is cleared For external faults the whole board is stopped using the shutdown sequencing described earlier In this case the system will also h...

Page 14: ...Protection OCP The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output MOSFETs For a complete description of the OCP circuitry please refer to the IRS2092S datasheet Here is a brief description Low Side Current Sensing Fig 15 shows the low side MOSFET as is protected from an overload condition by measuring the low side MOSFET drain to source voltage during th...

Page 15: ...divider R43 R25 and R41 for Ch1 can be used to program a higher threshold An additional external reverse blocking diode D1 for CH1 is required to block high voltage feeding into the CSH pin during low side conduction By subtracting a forward voltage drop of 0 6V at D1 the minimum threshold which can be set for the high side is 0 6V across the drain to source For IRAUDAMP5 the high side over curren...

Page 16: ... fault is removed Once the fault is cleared the green Normal LED will turn on There is no manual reset option Over Voltage Protection OVP Fig 18 OVP will shut down the amplifier if the bus voltage between GND and B exceeds 40V The threshold is determined by the voltage sum of the Zener diode Z105 R140 and VBE of Q109 As a result it protects the board from hazardous bus pumping at very low audio si...

Page 17: ...age sum of the Zener diode Z107 R145 and VBE of Q110 As with OVP UVP will automatically reset after three seconds and only one of the two supply voltages needs to be monitored Speaker DC Voltage Protection DCP Fig 19 DCP is provided to protect against DC current flowing into the speakers This abnormal condition is rare and is likely caused when the power amplifier fails and one of the high side or...

Page 18: ...t From CH2 Output B To DCP Fig 19 Efficiency Figs 20 demonstrate that IRAUDAM5 is highly efficient due to two main factors a DirectFETs offer low RDS ON and very low input capacitance and b The PWM operates as Pulse Density Modulation 0 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 100 0 0 20 40 60 80 100 120 140 160 180 Output Power W Power Stage Efficiency Efficiency vs Output Power 4Ω Single C...

Page 19: ...B supply 35V 4Ω Load 1kHz audio signal Temp ambient 25 C Fig 21 Click and POP noise One of the most important aspects of any audio amplifier is the startup and shutdown procedures Typically transients occurring during these intervals can result in audible pop or click noise from the output speaker Traditionally these transients have been kept away from the speaker through the use of a series relay...

Page 20: ...f the IRS2092S this is all that is required for complete sequencing The startup and shutdown timing diagrams are show in Figure 22A below Click Noise Reduction Sequencing at Trip and Reset Fig 22A For startup sequencing the control power supplies start up at different intervals depending on the B supplies As the B supplies reach 5 volts and 5 volts respectively the 5V control supplies for the anal...

Page 21: ...is muted It is then possible to shutdown the Class D stage CSD reaches two thirds VDD This process takes less than 200ms Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing Fig22B For any external fault condition OTP OVP UVP or DCP see Protection that does not lead to power supply shutdown the system will trip in a similar manner as described above Once the fault is cleared t...

Page 22: ...signer should place a set of external bus capacitors having enough capacitance to handle the audio ripple current Overall regulation and output voltage ripple for the power supply design are not critical when using the IRAUDAMP5 Class D amplifier as the power supply rejection ratio PSRR of the IRAUDAMP5 is excellent as shown on Figure 23 below Power Supply Rejection Ratio Green IRAUDAMP5 Cyan VAA ...

Page 23: ...Speaker Output Pink Negative Rail voltage B Fig 24 Input Signal A proper input signal is an analog signal below 20 kHz up to 3 5V peak having a source impedance of less than 600 ohms A 30 60 kHz input signal can cause LC resonance in the output LPF resulting in an abnormally large amount of reactive current flowing through the switching stage especially at 8 ohms or higher impedance towards open l...

Page 24: ...ed and controlled by the volume control IC U_2 setting the gain from the microcontroller IC U_1 The maximum volume setting clockwise rotation corresponds to a total gain of 37 9dB 78 8V V The total gain is a product of the power stage gain which is constant 23 2dB and the input stage gain that is directly controlled by the volume adjustment The volume range is about 100dB with minimum volume setti...

Page 25: ... VAA LP Filter LP Filter B CH2 C22 1 R32 CH1 C21 R31 COM Integrator Modulator and Shift level GND COM Integrator Modulator and Shift level GND D6 D8 D7 10k 1 D5 IRF6645 Q6 IRF6645 Q3 IRF6645 Q5 IRF6645 Q4 Bridged configuration Fig 27 Output Filter Design Preamplifier and Performance The audio performance of IRAUDAMP5 depends on a number of different factors The section entitled Typical Performance...

Page 26: ... R55 0 0 R56 0 0 Feedback Audio in Audio in R71 OPEN R72 OPEN 1 2 3 4 5 6 J1A 7 8 9 10 11 12 J1B ZCEN 1 CS 2 SDATAI 3 VD 4 DGRD 5 SCLK 6 SDATAO 7 MUTE 8 AINL 16 AGNDR 10 AOUTL 14 VA 13 VA 12 AOUTR 11 AGNDL 15 AINR 9 U_ CS3310 Feedback IRS2092S MODULE Preamplifier Fig28 It is possible to evaluate the performance without the preamp and volume control by moving resistors R13 and R14 to R71 and R72 re...

Page 27: ...all the error in the audible frequency range is shifted to the inaudible upper frequency range by nature of its operation Also sigma delta modulation allows a designer to apply a sufficient amount of correction The self oscillating frequency Fig 30 is determined by the total delay time inside the control loop of the system The delay of the logic circuits the IRS2092S gate driver propagation delay ...

Page 28: ...r have them separated by at least 25kHz With the installed components it is possible to change the self oscillating frequency from about 300kHz up to 450kHz as shown on Fig 30 Switches and Indicators There are four different indicators on the reference design as shown in the figure 31 below 1 An orange LED signifying a fault shutdown condition when lit 2 A green LED on the motherboard signifying c...

Page 29: ...0V R117 47R R118 1k LED Switches and Sync frequencies Fig 31 Switching Frequency Lock Synchronization Feature For single channel operation the use of the self oscillating switching scheme will yield the best audio performance The self oscillating frequency however changes with the duty ratio This varying frequency can interfere with AM radio broadcasts where a constant switching frequency with its...

Page 30: ... but the increase in THD seems independent from the clock frequency Therefore a 300 kHz clock frequency is recommended as shown on Fig 34 It is possible to improve the THD performance by increasing the corner frequency of the high pass filter HPF R17 and C15 for Ch1 Fig 33 that is used to inject the clock signal as shown in Figure 33 below This drop in THD however comes at the cost of reducing the...

Page 31: ... adjusted by setting potentiometer R113 INT FREQ If external EXT clock signal is selected a 0 5V square wave 50 duty ratio logic signal must be applied to BNC connector J17 0 001 10 0 002 0 005 0 01 0 02 0 05 0 1 0 2 0 5 1 2 5 100m 200 200m 500m 1 2 5 10 20 50 100 W Red CH1 Self Oscillator 400kHz Pink CH1 Sync Oscillator 400kHz Blue CH1 Sync Oscillator 450kHz Cyan CH1 Sync Oscillator 350kHz THD N ...

Page 32: ... R26 4 7R C17 0 1uF R37 1R R31 100K Rp1 100C B C28 47nF R48 1K R47 100K Q7 OTP CH1 R52 open R50 open LO 11 VS 13 HO 14 VCC 12 GND 2 VAA 1 COM 10 DT 9 OCSET 8 IN 3 COMP 4 CSD 5 VSS 6 VREF 7 VB 15 CSH 16 U1 IRS2092S C1 1nF C30 10nF CH1 Output to LPF1 35V Bus 35V Bus 5V 5V Audio Gnd 1 SD 35V Bus 35V Bus VAA VSS IN 1 CH1 O B CH1 B OTP1 OC Rp1 is thermally connected with Q3 C3 10uF C32 0 1uF 100V 3 2 1...

Page 33: ...VCC R45 4 7K D2 VSS VAA C16 3 3uF 10uF C11 C24 1nF 1250V C22 1nF 250V CH2 R23 4 7R C13 0 1uF R38 1R R51 open LO 11 VS 13 HO 14 VCC 12 GND 2 VAA 1 COM 10 DT 9 OCSET 8 IN 3 COMP 4 CSD 5 VSS 6 VREF 7 VB 15 CSH 16 U2 IRS2092S C2 1nF CH2 Output to LPF2 35V Bus 35V Bus 5V 5V Audio Gnd 2 SD 35V Bus 35V Bus SD PWM2 VCC CH2 O B CH2 B B OTP1 OTP2 OTP2 Rp2 is thermally connected with Q5 C4 10uF C33 0 1uF 100...

Page 34: ...R R27 10R R6 3 3K R42 10k R44 0 0 R29 10K C15 0 1uF 100V C19 3 3uF R39 33k B B SD IN 2 VCC R45 4 7K D2 5V VAA GND2 C16 3 3uF 10uF C11 R22 1k C24 1nF 1250V C22 1nF 250V CH2 R23 4 7R C13 0 1uF R38 1R R51 open LO 11 VS 13 HO 14 VCC 12 GND 2 VAA 1 COM 10 DT 9 OCSET 8 IN 3 COMP 4 CSD 5 VSS 6 VREF 7 VB 15 CSH 16 U2 IRS2092S C2 1nF CH2 Output to LPF2 35V Bus 35V Bus 5V 5V Audio Gnd 2 SD 35V Bus 35V Bus V...

Page 35: ...3310S06S R108 C107 4 7uF 16V C108 10nF 50V SCLK SDATAI C109 4 7uF 16V CS 5V Control Volume R55 0 0 R56 0 0 IRS2092S_ MODULE CH1 Feedback CH2 Feedback 5V Audio in Audio in ZM4732ADICT Z102 4 7V R104 47R 1W C103 10uF 50V IN GND OUT U_5 MC79M05 C102 10uF 50V R102 47R 1W C101 10uF 50V Vin GND Vout U_4 MC78M05 ZM4732ADICT Z101 4 7V D102 MA2YD2300 D101 MA2YD2300 C104 10uF 50V R101 47R 1W R103 47R 1W B 5...

Page 36: ...C14 R120 100R C114 10nF 50V 5V I E S SW S3A SW 3WAY_A B R109 1K R110 100k C110 1nF 50V C112 1200pF 50V D103 1N4148 CLK R116 47R CLK I E S SW S3B SW 3WAY_A B EXT CLK A24497 J8 BNC R115 47R R114 100R R113 5K POT R112 820R C111 100pF 50V Q103 MMBT5551 2 1 S2 SW_H L R111 10K C113 100pF 50V R134 10k R117 47R R143 10K SP MUTE R118 1k R129 6 8k C115 10uF 50V B R140 10k Z105 39V DC protection OVP R132 47k...

Page 37: ...Y C20 0805 open 1 open C30 C31 0805 10nF 50V X7R 2 PCC103BNCT ND DIGI KEY D1 D2 SOD 323 BAV19WS 7 F 2 BAV19WS FDICT ND DIGI KEY D3 D4 SOD 323 1N4148WS 7 F 2 1N4148WS FDICT ND DIGI KEY D5 D6 SMA MURA120T3G 2 MURA120T3GOSCT ND DIGI KEY D7 SMA ES1D 1 ES1DFSCT ND DIGI KEY DS1 DS2 805 LTST C171TBKT 2 160 1645 1 ND DIGI KEY J1A CON EISA31 CON EISA31 1 A26568 ND DIGI KEY J1B CON EISA31 CON EISA31 1 A2656...

Page 38: ...k RHM1 2KARCT ND DIGI KEY R21 R22 0805 1k 2 P1 0KACT ND DIGI KEY R23 R26 0805 4 7R 2 P4 7ACT ND DIGI KEY R25 R29 R36 R41 R42 0805 10K 5 P10KACT ND DIGI KEY R37 R38 0805 1R 3 P1 0ACT ND DIGI KEY R39 R40 0805 33K 3 RHM33KARCT ND DIGI KEY R43 R44 0805 0 3 RHM0 0ARCT ND DIGI KEY R49 R50 R51 R52 1206 open 3 open Rp1 Rp2 805 100C 3 594 2322 675 21007 MOUSER P1 P2 ST 32 3mm SQ 1k ST32ETB102TR ND DIGI KEY...

Page 39: ...A J2B 2 CON_POWER CON_POWER A26454 ND Digikey 28 J3 J4 2 MKDS5 2 9 5 277 1022 277 1271 ND or 651 1714971 Digikey or Mouser 29 J5 J6 2 Blue RCA RCJ 055 CP 1422 ND Digikey 30 J7 1 J HEADER3 277 1272 277 1272 ND or 651 1714984 Digikey or Mouser 31 J8 1 BNC_RA CON BNC A32248 ND Digikey 32 J9 1 ED1567 ED1567 ED1567 Digikey 33 L1 L2 2 Inductor from Panasonic ETQA21ZA220 or ETQA17B220 P13504 ND Digikey 3...

Page 40: ...420 Newark 77 U_2 1 N8A 3310S06S 3310 IR01 Tachyonix 78 U_3 1 M14A 74HC14 296 1194 1 ND Digikey 79 U_4 1 TO 220 MC78M05CTG MC78M05CTGOS ND Digikey 80 U_5 1 TO 220 LM79M05CT LM79M05CT ND Digikey 81 U_6 1 TO 220 LM78M12CT LM78M12CT ND Digikey 82 Z1 Z2 Z103 3 SOD 123 15V BZT52C15 FDICT ND Digikey 83 Z101 Z102 2 SMA 4 7V 1SMA5917BT3GOSCT ND Digikey 84 Z104 1 SOD 123 24V BZT52C24 FDICT ND Digikey 85 Z1...

Page 41: ...houlder Washer 3 Flat Washer 4 4 No 4 40 UNC 2B Hex Nut 5 No 4 40 UNC 2A X 1 2 Long Phillips Pan Head Screw 6 Lockwasher No 4 7 Heatsink 8 PCB 8 7 Item Description 1 Insulator Thermalfilm 2 Shoulder Washer 3 Flat Washer 4 4 No 4 40 UNC 2B Hex Nut 5 No 4 40 UNC 2A X 1 2 Long Phillips Pan Head Screw 6 Lockwasher No 4 7 Heatsink 8 PCB 8 7 ...

Page 42: ...er board Layer Stack Daughter board Material FR4 UL 125 C Layer Stack 2 Layers 1 oz Cu each Through hole plated Dimensions 3 125 x 1 52 x 0 062 Solder Mask LPI Solder mask SMOBC on Top and Bottom Layers Plating Open copper solder finish Silkscreen On Top and Bottom Layers Motherboard Material FR4 UL 125 C ...

Page 43: ...1 oz Cu Dimensions 5 2 x 5 8 x 0 062 Solder Mask LPI Solder mask SMOBC on Top and Bottom Layers Plating Open copper solder finish Silkscreen On Top and Bottom Layers IRAUDAMP5 PCB layers Class D Daughter board Figure 40 PCB Layout Top Side Solder Mask and Silkscreen ...

Page 44: ...www irf com Page 43 of 50 IRAUDAMP5 REV 3 1 Figure 41 PCB Layout Bottom Layer and Pads and bottom silk screen ...

Page 45: ...www irf com Pa Figure 39 PCB Layout Motherboard ge 44 of 50 IRAUDAMP5 REV 3 1 Top Layer ...

Page 46: ...www irf com Top silk screen Page 45 of 50 IRAUDAMP5 REV 3 1 ...

Page 47: ...www irf com Page 46 of 50 IRAUDAMP5 REV 3 1 Bottom ...

Page 48: ...www irf com Page 47 of 50 IRAUDAMP5 REV 3 1 4 0 ...

Page 49: ...www irf com Page 48 of 50 IRAUDAMP5 REV 3 1 Bottom Silkscreen 4 0 ...

Page 50: ...escription Date 3 0 Released 7 27 07 3 1 Schematic error marked on red pages 31 33 R25 and R29 was connected to CSH Fig 40 and Fig 41 updated 1 28 08 WORLD HEADQUARTERS 233 Kansas St El Segundo California 90245 Tel 310 252 7105 Data and specifications subject to change without notice 7 27 2007 ...

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