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© 2011 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,
Rev. 3.
To locate any updates for this document, refer to the
MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.
Document Number: MPC8360EEC
Rev. 4, 01/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . 13
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 17
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 20
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 28
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11. I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 62
19. HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
21. Package and Pin Listings . . . . . . . . . . . . . . . . . 68
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
24. System Design Information . . . . . . . . . . . . . . 102
25. Ordering Information . . . . . . . . . . . . . . . . . . . 106
26. Document Revision History . . . . . . . . . . . . . 107
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications