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TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip
Select pin.

Preliminary

July 19, 2001

Revision 1.03

DESIGNING THE XRT71D00 AND THE XRT73L00

DEVICES TO OPERATE IN THE HOST MODE, AND TO

BE ACCESSED VIA A SINGLE CHIP SELECT PIN

Summary of Contents for XRT71D00

Page 1: ...Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 1 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE...

Page 2: ...NMENT FEATURE OF THE XRT71D00 DEVICE 9 4 0 HARDWARE DESIGN CONSIDERATIONS 12 4 1 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE RECEIVE PATH 15 4 2 DESIGN CONSIDERATIONS WHEN THE...

Page 3: ...that one can use to interface the XRT71D00 DS3 E3 STS 1 Jitter Attenuator to the XRT73L00 DS3 E3 STS 1 LIU IC while operating each device in the Host Mode In particular this Applications Note describ...

Page 4: ...perate in the Hardware Mode then the user can configure the XRT73L00 device into a wide variety of modes via the following external input pins REQDIS Receive Equalizer Enable Disable Input pin TXLEV T...

Page 5: ...lock In CS Chip Select Input REG_RESET Register Reset Input A more detailed description of each of these pins is presented in Appendix C Therefore for Host Mode operation the XRT73L00 device provides...

Page 6: ...Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS 0x03 CR3 R W RNRZ LOSMUT RCLK2 LCV RCLK2INV RCLK1INV 0x04 CR4 R W Reserved STS 1 DS3 E3 LLB RLB 0x05 CR5 R W Reserved Reserved Reserved Reserved Reserved 0x06...

Page 7: ...e user can configure the XRT71D00 device into a wide variety of modes via the following external input pins FSS FIFO Size Select DJA Disable Jitter Attenuator PLL Select CLKES Clock Edge Select BWS Ji...

Page 8: ...in Figure 2 Register Bit Format Addr Command Register Type D6 D5 D4 D3 D2 D1 D0 Channel 0 Registers 0x06 CR6 R W STS 1 0 E3 DS3 DJA BWS CLKES FSS 0x07 CR7 R O Reserved Reserved Reserved Reserved Rese...

Page 9: ...IU IC and 2 XRT71D00 DS3 E3 STS 1 Jitter Attenuator Devices 1 XRT73L03 3 Channel DS3 E3 STS 1 LIU IC and 3 XRT71D00 DS3 E3 STS 1 Jitter Attenuator Devices Figure 2 presents the bit format of the Comma...

Page 10: ...ly ignore these particular operations and will continue to tri state its SDO output pin Similarly if a given XRT71D00 device is assigned to Channel 1 then it will only respond to READ WRITE operations...

Page 11: ...s Res Res ENDECDIS ALOSDIS DLOSDIS REQDIS 0x03 CR3 R W Res Res RNRZ LOSMUT RCLK2 LCV RCLK2 INV RCLK1 INV 0x04 CR4 R W Res Res Res STS 1 DS3 E3 LLB RLB 0x05 CR5 R W Res Res Res Res Res Res Res 0x06 CR6...

Page 12: ...the XRT73L00 device Therefore pulsing the HW_RESET input signal low will command a Hardware RESET to both the Jitter Attenuator and the LIU IC b JA_LIU_CS This signal is tied to the CS Chip Select in...

Page 13: ...ter this prevents the XRT71D00 device from pulling the entire JA_LIU_SDO_OUT line to GND and corrupting the data that needs to be read via from the XRT73L00 LIU Device Unfortunately the XRT73L00 LIU I...

Page 14: ...RPOS RNEG and RCLK output signals from the XRT73L00 LIU IC are being routed to the RPOS RNEG and RCLK input signals of the XRT71D00 Jitter Attenuator IC 3 The XRT71D00 device has been designed to oper...

Page 15: ...e are met By default the XRT73L00 device will update its recovered data via the RPOS and RNEG output pins upon the rising edge of RCLK1 and RCLK2 According to the XRT73L00 Data Sheet the RCLK to RPOS...

Page 16: ...XRT73L00 Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 16 FIGURE 4 SCHEMATIC DESIGN OF XRT71D00 DEVICE BEING INTERFACED TO...

Page 17: ...EG RRPOS VDDD Ch_Addr_0 CS VDDD C8 0 1uF C9 0 1uF J1 BNC 1 2 J2 BNC 1 2 R4 37 4 R5 37 4 JP1 JUMPER 1 2 T1 T3001 1 6 3 4 L1 15uH T2 T3001 1 6 3 4 C11 1000pF L2 6 8uH L3 6 8uH D1 D1N5914 U10 XRT73L00 1...

Page 18: ...O Res Res Res Res Res Res FL Figure 5 The Recommended Bit Format of the Composite Set of Command Registers from the XRT73L00 and the XRT71D00 Device when the XRT71D00 device is configured to operate...

Page 19: ...ice are met By default the XRT73L00 device will sample the data input at the TPDATA TNDATA pins upon the falling edge of TCLK According to the XRT73L00 Data Sheet the TPDATA TNDATA to TCLK set up time...

Page 20: ...RT73L00 Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 19 FIGURE 6 SCHEMATIC DESIGN OF XRT71D00 DEVICE BEING INTERFACED TO T...

Page 21: ...R14 274 R15 274 JP3 JUMPER 1 2 R16 31 6 JP4 JUMPER 1 2 R17 31 6 R18 100 R19 100 U11 XRT71D00 31 2 3 4 5 6 7 8 10 11 14 15 18 19 20 21 22 23 26 27 28 29 30 RPOS RNEG RCLK GNDD MCLK GNDA VDDA STS 1 SDI...

Page 22: ...Res Res Res Res FL Figure 7 The Recommended Bit Format of the Composite Set of Command Registers from the XRT73L00 and the XRT71D00 Device when the XRT71D00 device is configured to operate in the Tran...

Page 23: ...RT71D00 device is also a mixed signal device This particular device consists of an Analog and Digital PLL Each of these PLLs is used to generate high speed signals that support loop filtering within t...

Page 24: ...Pin 7 is the Analog power supply pin Pins 27 and 30 are the digital power supply pins The Receive Analog Power supply pin e g pin 10 of the LIU is the most critical as it powers the Clock Recovery PLL...

Page 25: ...erefore the user should select a 15uH inductor that has a DC resistance of less than 0 294 An example of an acceptable inductor for L1 is the 4922 15L from API Delevan This particular inductor has a m...

Page 26: ...nd C4 are used to filter and isolate the power supply line going to the LIU Receive Analog VDD Jitter Attenuator Analog VDD pins and the LIU Transmit Analog VDD pins Each of these inductors should be...

Page 27: ...of size 1210 from API Delevan The 1210 682J inductor is spec d to have a maximum dc resistance of 1 8 ohms Additionally the 1210 682J inductor has a maximum current rating of 321mA The S1210 682K ind...

Page 28: ...and routing of these decoupling capacitors must be such to minimize the trace length and in turn inductance between the capacitor and the corresponding VDD pin and the capacitor and the corresponding...

Page 29: ...the BNC Connector Shield to GND The characteristics of a capacitor to be used in this role are as follows This capacitor must be rated for high voltages This capacitor must impose minimum AC impedance...

Page 30: ...XRT71D00 and the XRT73L00 Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 28 APPENDIX A REGISTER DESCRIPTION FOR THE XRT73L0...

Page 31: ...ved Reserved Reserved Reserved Reserved Figure A1 The Bit Format of the Command Registers within the XRT73L00 Device A brief description definition of each of these bit fields are presented below Comm...

Page 32: ...s of Signal This Read Only bit field indicates whether or not the Digital LOS Detector is currently declaring an LOS condition If this bit field is set to 1 then the Digital LOS Detector is currently...

Page 33: ...r not the Clock Recovery PLL within the Receive Section of the LIU IC is declaring a Loss of Lock condition or not If the Clock Recovery PLL is currently declaring a Loss of Lock condition then it wil...

Page 34: ...ignored NOTE If the user configures the Transmit Section of the LIU to operate in the Single Rail Mode then is imperative that the user to enable both the B3ZS HDB3 Encoder and Decoder blocks by sett...

Page 35: ...es pattern onto the line Setting this bit field to 0 configures the Transmit Section to transmit data based that which is sampled via the TPDATA TNDATA input pins Bit D4 TXOFF Transmit Shut OFF This R...

Page 36: ...D1 DLOSDIS Digital LOS Detector Disable This Read Write bit field permits the user to enable or disable the Digital LOS Detector within the LIU IC Setting this bit field to 0 enables the Digital LOS...

Page 37: ...e LIU to update the RPOS and RNEG output pins upon the rising edge of the RCLK1 signal Conversely setting this bit field to 1 configures the LIU to update the RPOS and RNEG output pins upon the fallin...

Page 38: ...ding upon the state of the D0 RCLK1 bit field Bit D3 LOSMUT MUTING upon LOS Enable Disable This Read Write bit field permits the user to enable or disable the MUTing upon LOS feature within the XRT73L...

Page 39: ...e Normal Operation 0 1 Analog Local Loop back Mode 1 0 Remote Loop back Mode 1 1 Digital Local Loop back Mode Bit D1 LLB Loop back Select This Read Write bit field along with D0 RLB permits the user t...

Page 40: ...te in either the DS3 or the STS 1 Modes In this setting the state of the D3 STS 1 DS3 bit field will dictate whether the chip is operating in the DS3 or STS 1 Mode Bit D3 STS 1 DS3 STS 1 or DS3 Mode S...

Page 41: ...00 and the XRT73L00 Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 39 APPENDIX B REGISTER DESCRIPTION FOR THE XRT71D00 DS3 E...

Page 42: ...Reserved Reserved Reserved Reserved Reserved FL Channel 2 Registers 0x16 CR22 R W STS 1 0 E3 DS3 DJA BWS CLKES FSS 0x17 CR23 R W Reserved Reserved Reserved Reserved Reserved Reserved FL Figure B1 The...

Page 43: ...state of the RPOS RNEG input pins upon the falling edge of the RCLK input signal b To update the output data via the RRPOS RRNEG output pins upon the rising edge of the RRCLK output signal D2 BWS Band...

Page 44: ...itter Attenuator PLL Conversely setting this bit field to 1 disables the Jitter Attenuator PLL D4 E3 DS3 Data Rate Select This Read Write bit field along with bit D6 STS 1 permits the user to configur...

Page 45: ...claring a FIFO Alarm event If the FIFO READ and WRITE pointers come within two bit positions or each other then the XRT71D00 device will declare a FIFO Alarm event The purpose of this FIFO Alarm event...

Page 46: ...the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode and to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 44 APPENDIX C DESCRIPTION OF MICROPROCESSOR SER...

Page 47: ...is input pin e g pull it LOW in order to enable communication with the XRT71D00 or the XRT73L00 device via the Microprocessor Serial Interface NOTE If this input pin is HIGH then all data being applie...

Page 48: ...specified Command Register during READ operations Data which is output via this pin is updated upon the falling edge of the SCLK input signal This output pin is tri stated during all other times REG_R...

Page 49: ...the user The user provides this information to the Microprocessor Serial Interface by writing eight serial bits of data into the SDI input Note each of these bits will be clocked into the SDI input on...

Page 50: ...the data contents of the addressed Command Register at Address A3 A2 A1 A0 via the SDO output pin The Microprocessor Serial Interface will output this five bit data word D0 through D4 in ascending or...

Page 51: ...lect pin Preliminary July 19 2001 Revision 1 03 49 CSB SCLK R W A0 A1 A2 A3 0 0 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 0 0 0 SDO High Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Denotes a Don t Care V...

Page 52: ...to be accessed via a single Chip Select pin Preliminary July 19 2001 Revision 1 03 50 APPENDIX D CONTACT INFORMATION FOR API DELEVAN Corporate Office API Delevan 270 Quaker Road East Aurora NY 14052...

Page 53: ...iously missing CHANGES FROM REVISION 1 01 TO 1 02 Corrected Schematic in Figure 4 in order to have the RxAVDD pins of the XRT73L00 LIU connect to the RxAVDD off page connector of the schematic Likewis...

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