Epson S1D15722 Series Technical Manual Download

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Rev.1.1

S1D15722D01B000

Technical Manual

Summary of Contents for S1D15722 Series

Page 1: ...Rev 1 1 S1D15722D01B000 Technical Manual ...

Page 2: ...Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Ex...

Page 3: ...Configuration of product number zDEVICES S1 D 15722 D 01B 000 Packing specifications Specifications Shape D Chip T TCP F QFP Model number Model name D LCD Driver Product classification S1 Semiconductors ...

Page 4: ...Chip Select 14 6 1 5 Accessing Display Data RAM and Internal Register 14 6 2 Display Data RAM 16 6 2 1 Display Data RAM 16 6 2 2 Gray Scale Display 17 6 2 3 Page Address Circuit Column Address Circuit 17 6 2 4 Line Address Circuit 17 6 2 5 I O Buffer Circuit 18 6 2 6 Display Data Latch Circuit 18 6 3 Oscillation Circuit 21 6 4 Display Timing Signal Generator 21 6 5 Operating State Detector Circuit...

Page 5: ...7 9 4 Temperature Sensor Characteristics 58 9 4 1 Analog Voltage Output Characteristics 58 10 TIMING CHARACTERISTICS 59 10 1 System Bus Read Write Characteristics 1 80 Series MPU 59 10 2 System Bus Read Write Characteristics 2 68 Series MPU 61 10 3 Serial Interface 63 10 4 Display Control I O Timing 64 10 5 Reset Input Timing 65 10 6 Temperature Sensor Measuring Timing 65 11 POWER CIRCUIT REFERENC...

Page 6: ... Required external LCD bias voltages input The S1D15722 series provides both FRM 4 grayscale display and binary display With display data RAM 224 184 2 bits incorporated for 4 grayscale display 2 bits of built in RAM correspond to 1 dot of pixel and for binary display 1 bit of the built in RAM corresponds to 1 dot of pixel The S1D15722 series contains 184 circuits of common output and 224 circuits...

Page 7: ... be directly connected to MPU of both 80 and 68 series serial interface Extensive command functions Display lines set n line inversion display data RAM address control gray scale control display ON OFF display in forward reverse direction full display lighting ON OFF display clock built in oscillation circuit control select common output status etc Required external LCD bias voltages input Built i...

Page 8: ...ternal logic power supply circuit Display data latch circuit Command decoder Bus holder Column address DDRAM 224 184 2 SEG Drivers CLS x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x SEG0 ____ RES ___ WR R __ W ___ RD E A0 P S SI SCL D7 to D0 I O buffer FR CL M S SYNC DOF _______ F1 F2 COM decoder SEG Decoder VSSL VDD V1 MV1 MV2 C86 MPU Interface Temperature sensor circuit SV...

Page 9: ...m 6 to 17 19 to 44 83 85 to 98 90 109 µm 18 48 to 82 84 90 60 µm 45 to 47 90 45 µm 99 to 153 45 85 µm 154 to 481 90 35 µm Bump size PAD No 482 to 531 45 85 µm Bump height Typ 17 µm 4 2 Alignment mark Alignment coordinate 1 1500 0 9380 0 µm 2 1500 0 9380 0 µm Mark size a 15 µm b 45 µm Mark 1 Mark 2 b b a a a a a a 104 482 153 0 0 531 1 103 481 154 5 6 99 98 D157MD1B Die No Alignment Mark2 Alignment...

Page 10: ...8 5 71 D5 3180 0 121 COM76 465 0 22 TEST11 5772 5 72 D6 3270 0 122 COM75 403 0 23 TEST12 5448 5 73 D7 3540 0 123 COM74 341 0 24 TEST12 5322 5 74 VDD 3630 0 124 COM73 279 0 25 TEST9 4998 5 75 M S 3720 0 125 COM72 217 0 26 TEST9 4872 5 76 CLS 3990 0 126 COM71 155 0 27 VDD2 4510 7 77 VSSL 4080 0 127 COM70 93 0 28 VDD2 4384 7 78 TEST 4260 0 128 COM69 31 0 29 VDD2 4258 7 79 C86 4350 0 129 COM68 31 0 30...

Page 11: ... 272 SEG66 2821 0 173 COM28 8959 0 223 SEG17 5859 0 273 SEG67 2759 0 174 COM27 8897 0 224 SEG18 5797 0 274 SEG68 2697 0 175 COM26 8835 0 225 SEG19 5735 0 275 SEG69 2635 0 176 COM25 8773 0 226 SEG20 5673 0 276 SEG70 2573 0 177 COM24 8711 0 227 SEG21 5611 0 277 SEG71 2511 0 178 COM23 8649 0 228 SEG22 5549 0 278 SEG72 2449 0 179 COM22 8587 0 229 SEG23 5487 0 279 SEG73 2387 0 180 COM21 8525 0 230 SEG2...

Page 12: ... 422 SEG216 6479 0 323 SEG117 341 0 373 SEG167 3441 0 423 SEG217 6541 0 324 SEG118 403 0 374 SEG168 3503 0 424 SEG218 6603 0 325 SEG119 465 0 375 SEG169 3565 0 425 SEG219 6665 0 326 SEG120 527 0 376 SEG170 3627 0 426 SEG220 6727 0 327 SEG121 589 0 377 SEG171 3689 0 427 SEG221 6789 0 328 SEG122 651 0 378 SEG172 3751 0 428 SEG222 6851 0 329 SEG123 713 0 379 SEG173 3813 0 429 SEG223 6913 0 330 SEG124...

Page 13: ...516 COM170 589 0 467 COM125 9269 0 517 COM171 651 0 468 COM126 9331 0 518 COM172 713 0 469 COM127 9393 0 519 COM173 775 0 470 COM128 9455 0 520 COM174 837 0 471 COM129 9517 0 521 COM175 899 0 472 COM130 9579 0 522 COM176 961 0 473 COM131 9641 0 523 COM177 1023 0 474 COM132 9703 0 524 COM178 1085 0 475 COM133 9765 0 525 COM179 1147 0 476 COM134 9827 0 526 COM180 1209 0 477 COM135 9889 0 527 COM181 ...

Page 14: ... I This pin is used for making the VDI generating circuit valid or invalid VDIS HIGH The VDI generating circuit is valid Master chip VDIS LOW The VDI generating circuit is invalid Slave chip When the VDIS pin is used by changing from LOW to HIGH it should be initialized by the pin after changing it Only the VDIS pin controls operation of the VDI generating circuit and the circuit operates independ...

Page 15: ...CS I Chip select signal Active when ___ CS LOW enabling input or output of data command When ___ CS HIGH data bus are set to Hi Z 1 ___ RD E I When MPU of the 80 series is connected Active LOW This pin connects ___ RD signal of 80 series MPU Data bus enters a state of output while this signal is set to LOW When MPU of the 68 series is connected Active HIGH Becomes enable clock input pin of the 68 ...

Page 16: ...timing signal required for LCD display and slave operation inputs timing signal required for LCD display This causes synchronization in LCD display system M S HIGH Master operation M S LOW Slave operation Sets as shown in the table below depending on the state of M S and CLS M S CLS Oscillation circult CL FR ____ DOF F1 F2 SYNC HIGH Enabled Output Output HIGH LOW Disabled Input Output HIGH Disable...

Page 17: ...n 1 5 4 Liquid Crystal Drive Pins Pin name I O Description Number of pins SEG0 to SEG223 O Liquid crystal segment drive output pin One level is selected from V2 V1 VC MV1 and MV2 by combining display RAM and FR F1 and F2 signals 224 in total COM0 to COM183 O Liquid crystal common drive output pin One level is selected from V3 VC and VSSL VSSL by combining scan data and FR F1 and F2 signals 184 in ...

Page 18: ...e 6 3 Common 68 series 80 series A0 R __ W ___ RD ___ WR Function 1 1 0 1 Display data reading reads status 1 0 1 0 Status data writing writes command parameter 0 0 1 0 Writes a command 6 1 3 Serial Interface When serial interface is selected P S LOW the chip is active ___ CS LOW and can accept serial data input SI and serial clock input SCL Serial interface is comprised of an 8 bit shift register...

Page 19: ... be taken for wiring termination reflection and external noise It is recommended to check operation using the actual equipment 6 1 4 Chip Select Since this IC has chip select pin parallel interface or serial interface is enabled when ___ CS LOW is set When the chip select is inactive D0 to D7 are in the state of high impedance and input of A0 ___ RD ___ WR SI and SCL is disabled When serial interf...

Page 20: ...Therefore read sequence of display data RAM is subject to constraints In the data read immediately after the display data read command the specified address data is not output dummy read but it is output at the 2nd data read session This relationship is shown in Fig 6 2 Fig 6 2 Read Sequence of Display Data RAM Write Read Dummy N 2 N 1 N Write command N 2 N 1 N ___ WR MPU DATA Latch BUS Holder Wri...

Page 21: ...ot of pixel When RAM bit data is 1 black display appears When RAM data is 0 white display appears RAM bit data 1 ON Black in normal display mode 0 OFF White in normal display mode Since display data D7 to D0 from MPU corresponds to the common direction of LCD as shown in Fig 6 3 and Fig 6 4 higher degree of freedom is achieved in configuring display with less constraints on display data transfer i...

Page 22: ... an access to Page45 the column address increments by 1 and the page address moves to Page0 In both address increment directions moves to the page address Page0 and the column address 0H after an access to the column address DFH of the page address Page 45 is made As shown in Table 6 4 the correspondence between the column address of the display data RAM and segment output can be reversed with the...

Page 23: ...he display data clutch circuit an asynchronous access made to the display data RAM during crystal liquid display does not have an adverse effect on display including flickering 6 2 6 Display Data Latch Circuit The display data latch circuit is a latch for temporarily storing data to be output to the liquid crystal drive circuit from the display data RAM Since the display normal inverted display ON...

Page 24: ... 0DH COM13 D5 D4 0EH COM14 0 0 0 0 1 1 D7 D6 Page 3 0FH COM15 D1 D0 10H COM16 D3 D2 11H COM17 D5 D4 12H COM18 0 0 0 1 0 0 D7 D6 Page 4 13H COM19 D1 D0 14H COM20 D3 D2 15H COM21 D5 D4 16H COM22 0 0 0 1 0 1 D7 D6 Page 5 17H COM23 D1 D0 B0H COM176 D3 D2 B1H COM177 D5 D4 B2H COM178 1 0 1 1 0 0 D7 D6 Page 44 B3H COM179 D1 D0 B4H COM180 D3 D2 B5H COM181 D5 D4 B6H COM182 1 0 1 1 0 1 D7 D6 Page 45 B7H COM...

Page 25: ...34 D3 23H COM35 0 0 0 1 0 0 D4 Page 4 24H COM36 D5 25H COM37 D6 26H COM38 D7 27H COM39 D0 A8H COM168 D1 A9H COM169 D2 AAH COM170 D3 ABH COM171 0 1 0 1 0 1 D4 Page 21 ACH COM172 D5 ADH COM173 D6 AEH COM174 D7 AFH COM175 D0 B0H COM176 D1 B1H COM177 D2 B2H COM178 D3 B3H COM179 0 1 0 1 1 0 D4 Page 22 B4H COM180 D5 B5H COM181 D6 B6H COM182 D7 B7H COM183 D0 B8H D1 B9H D2 BAH D3 BBH 0 1 0 1 1 1 D4 Page 2...

Page 26: ...e 6 5 Operating Mode CL FR SYNC F1 F2 ____ DOF Built in oscillation circuit enabled CLS HIGH Output Output Master M S HIGH Built in oscillation circuit disabled CLS LOW Input Output Built in oscillation circuit enabled CLS HIGH Input Input Slave M S LOW Built in oscillation circuit disabled CLS LOW Input Input 6 5 Operating State Detector Circuit This circuit detects an error if the state of a spe...

Page 27: ... 1 2 3 COM 4 5 6 7 COM 176 177 178 179 COM 180 181 182 183 State 2 Normal drive invert scan direction COM 183 182 181 180 COM 179 178 177 176 COM 7 6 5 4 COM 3 2 1 0 State 3 Interlace drive pattern A Scanning start position COM0 Normal scan direction COM 0 1 2 3 COM 92 93 94 95 COM 44 45 46 47 COM 136 137 138 139 COM 88 89 90 91 COM 179 181 182 183 State 4 Interlace drive pattern A Scanning start ...

Page 28: ...5 Interlace drive pattern B normal rotation of scanning direction Scan start position COM92 State 6 Interlace drive pattern B inverted scanning direction Scan start position COM91 Fig 6 7 Relationship between Select Common Output Status Command and LCD Panel Connection COM0 COM91 COM92 COM183 chip bottom view scanning direction COM0 COM91 COM92 COM183 chip bottom view scanning direction COM0 COM91...

Page 29: ...onic volume register value according to the temperature sensor output value from MPU and controlling the liquid crystal display voltage V3 6 7 1 Analog Voltage Output Inputting the temperature sensor ON command causes the analog voltage to be output from the SVD2 pin which varies according to the temperature To control liquid crystal drive voltage with higher accuracy configure the system which ca...

Page 30: ...ly To perform temperature detection accurately be sure to stop access from the MPU when capturing the temperature sensor output and comply with operating conditions specified at the AC timing 2 Influence of mounting The temperature sensor circuit analog output SVD2 is specified using the output voltage value for the IC s board potential VSS When measuring the SVD2 potential in the actual system at...

Page 31: ... SVD21 viewed from the IC s VDD defined in the specifications To eliminate the impact of V as much as possible adopt the design and usage with consideration given to three points below Decrease the resistance value between the system ground and IC s VSS pin as low as possible including ITO resistance when mounting COG Measure the temperature sensor output voltage with the current consumed by IC re...

Page 32: ...fy write OFF 17 Built in oscillation circuit stop 18 Clock frequency register D3 D2 D1 D0 0 1 0 0 19 TEST1 register D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 20 Discharge ON at the ____ RES LOW level only 21 Power saving reset OFF 23 Data in the register in the serial interface clear 24 Temperature sensor OFF 25 MLS drive select register D4 D3 0 1 N line frame inversion overlap OFF Non dispersive dr...

Page 33: ...s performed in synchronization with display clock input from the built in oscillation circuit or external source Do not stop clock frequency input from the built in oscillation circuit or external source during display ON E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 Output level 0 1 0 1 0 1 0 1 1 1 0 Display OFF 1 Display ON After resetting by the ____ RES pin the display is set to OFF 2 Disp...

Page 34: ...rn B normal scanning direction 1 1 1 Interlace drive pattern B inverted scanning direction 5 Set display start line With the parameter following this command specify the display start line address of the display data RAM shown in Figs 6 5 and 6 6 The display area appears in the incremental direction of the line address from the specified line address Dynamically changing the line address using thi...

Page 35: ...higher is not allowed II In the binary display mode P6 P5 P4 P3 P2 P1 P0 Line address 0 0 0 0 0 0 0 00H 4 0 0 0 0 0 0 0 1 04H 4 1 0 1 0 1 1 0 0 B0H 4 44 0 1 0 1 1 0 1 B4H 4 45 1 0 1 1 0 1 0 168H 4 90 1 0 1 1 0 1 1 16CH 4 91 Note After resetting by the ____ RES pin the line address is set to 00H Note Register setting at 1 0 1 1 1 0 0 or higher is not allowed Sequence of setting display start line F...

Page 36: ...0 2CH Page 44 1 0 1 1 0 1 2DH Page 45 Note After resetting by the ____ RES pin the address is set to 00H Note Register setting at 1 0 1 1 1 0 or higher is not allowed 7 Set column address This command specifies the column address of the display data RAM shown in Figs 6 5 and 6 6 For more information see 6 2 3 Page Address Circuit Column Address Circuit in FUNCTIONAL DESCRIPTION E R __ W A0 ___ RD ...

Page 37: ... ___ WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 Read data 10 Select display data input direction This command allows setting of the direction of automatic increment of the display RAM address For more information see 6 2 3 Page Address Circuit Column Address Circuit in FUNCTIONAL DESCRIPTION E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 Direction 0 1 0 1 0 0 0 0 1 0 0 Column 1 Page...

Page 38: ...he ____ RES pin the number of inverted lines is set to 4 Note Register setting at 1 0 1 1 1 0 or higher is not allowed 13 n line inverted drive ON FF This command allows ON OFF of the n line inverted drive E R __ W N line A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 inverted drive 0 1 0 1 1 1 0 0 1 0 0 OFF 1 ON Note After resetting by the ____ RES pin the n line inverted drive is set to OFF 14 Set dis...

Page 39: ...l P7 P6 P5 P4 P3 P2 P1 P0 1 0 0 1 Level 1 light Setting disabled 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 Level 14 dark 1 1 1 0 Setting disabled Note Set so that the density of gray scale bits 1 0 and 0 1 will not be reversed Note After resetting by the ____ RES pin the density is set to gray scale bit 1 0 0 1 0 1 and gray scale bit 0 ...

Page 40: ...he panel continuous COM pin in 4 lines Be sure to set both parameters continuously because this command uses both parameters of the display lines and start point block in a pair E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 0 1 1 0 1 1 0 1 Set mode 1 1 0 P15 P14 P13 P12 P11 P10 Display lines Set register 1 1 0 P25 P24 P23 P22 P21 P20 Set start point Set register Note An asterisk ...

Page 41: ...ter reset by RES pin the start point is below Common output state Normal driving Normal scan direction Block 0 Prohibit 1 0 1 1 1 0 or upper value Setup example of set the number of display line command Setup example 1 Select common output state normal drive normal scanning direction When the display is set to 88 lines and the start point is to 1 COM4 to 7 the display of 88 lines appears from COM4...

Page 42: ... address at the time of inputting the read modify write command This function lessens the load from MPU when repeatedly changing data in the specific display area like blinking cursor E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 The command other than read write display command can be used even in the read modify write mode The page address set command and column address...

Page 43: ...lt in oscillation circuit To turn off the built in oscillation circuit stop the built in power supply circuit and liquid crystal display circuit using the set power control command and display OFF command and then discharge the capacitor using the discharge ON command E R __ W Built in oscillation A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 circuit 0 1 0 1 0 1 0 1 0 1 0 OFF 1 ON 21 Select clock frequ...

Page 44: ...22 9 62 71 89 119 1 1 1 1 21 3 58 67 83 111 After resetting by the ____ RES pin it is set to 0 1 0 0 Indicates the typical value at 25 C 22 Discharge ON OFF This command allows the capacitor connected to the power supply circuit to be discharged which is required for the following instances When turning off the system power supply VDD VSS When changing the number of display lines See 4 When changi...

Page 45: ...ta RAM is accessible from MPU The power save OFF command is used to cancel the power saving condition and reset to the state prior to starting power save command In the power saving mode The built in oscillation circuit is stopped All the liquid crystal drive circuits are stopped VC level is output from all SEG COM The temperature sensor circuit and VDI generation circuit operate It is recommended...

Page 46: ...ead is given below Results of reading Description LOW Error not detected HIGH A bit flip of part of the command register occurred which could be a cause of disabled normal display Re execute all the commands The commands that support error detection of the register are Display ON OFF Built in oscillation circuit ON OFF Full display lighting ON OFF Display normal inverted TEST1 set The five command...

Page 47: ...0 Temperature sensor OFF 1 Temperature sensor ON After resetting by the ____ RES pin the temperature sensor is set to OFF Setting the temperature sensor to ON is no problem when the temperature sensor is not use However operating current of the temperature sensor is steadily consumed The temperature sensor circuit is controlled independently of the power save command To reduce current consumption ...

Page 48: ... by Select clock frequency command or external clock frequency 27 NOP Command for Non Operation E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 28 TEST1 Command for IC chip testing Do not use If this command is executed the IC goes into test mode If the IC goes into test mode by mistake execute the NOP command to clear test mode E R __ W A0 ___ RD ___ WR D7 D6 D5 D4 D3 D2 D...

Page 49: ...ne inverted drive register 1 1 0 Number of inverted lines Set the number of lines of n line inverted drive 13 n line inverted drive ON FF 0 1 0 1 1 1 0 0 1 0 0 1 n line inverted drive ON FF 0 OFF 1 ON 0 1 0 0 1 1 0 0 1 1 0 14 Set display mode 1 1 0 Mode Select 4 gray scale display binary display 00 4 gray scale 01 binary 0 1 0 0 0 1 1 1 0 0 1 Selects the density of the gray scale 15 Set gray scale...

Page 50: ... OFF 1 ON 26 Select MLS drive 1 1 0 0 0 0 P4 P3 0 1 1 P3 0 Dispersion 1 Non dispersion 27 NOP 0 1 0 1 1 1 0 0 0 1 1 Command for Non Operation 0 1 0 0 0 1 0 0 1 0 1 28 TEST1 0 1 0 0 0 0 0 0 0 0 0 Command for testing IC chip Prohibit 0 1 0 1 1 1 1 0 29 TEST2 0 1 0 1 1 1 1 1 1 1 1 Command for testing IC chip Prohibit 30 TEST3 0 1 0 1 0 0 0 1 1 1 1 Command for testing IC chip Prohibit ...

Page 51: ...OFF 4 Select common output state 5 Set display start line 11 Direction of setting column address 14 Set display mode 17 Set number of display lines 26 Select MLS drive The state of reset cancelled ____ RES pin HIGH 2 End of initial setting Setting functions by command input user configuration 12 Set n line inverted drive register 13 n line inverted drive ON FF Setting functions by command input us...

Page 52: ...external noise Likewise for the command used for setting the register value reset the register when performing initial setting and refreshing even if default values after reset are used as they are 4 LCD voltages V3 to MV2 are sure to supply all at the same timing 2 Data display 1 Reset the register when performing initial setting and refreshing even if it is set to use default values as they are ...

Page 53: ... Initial setting reference 2 2 Data display reference 3 When the IC chip enters the power saving mode the power save OFF command can be used to exit 4 When the IC chip goes into power saving mode the discharge OFF command can be used to exit 5 When the IC chip goes into read modify write mode the end command can be used to exit 6 When the IC chip goes into test mode the NOP command can be used to ...

Page 54: ...s Set functions by command input user configuration 23 Power save ON 1 Set functions by command input user configuration 22 Discharge ON 2 Set functions by command input user configuration 17 Set number of display lines 21 Set clock frequency 3 12 Set n line inverted drive register 4 Set functions by command input user configuration 22 Discharge OFF Set functions by command input user configuratio...

Page 55: ...F sequence 1 The threshold voltage of the LCD panel 1 V serves as an index Prevent VDD and VDD2 from becoming high impedance during discharge reset Optional state VDD VDD2 power supply OFF Set functions by command input user configuration 23 Power save ON Set functions by command input user configuration 22 Discharge ON External power supply stop Set the time tL from entering the state of reset to...

Page 56: ...ply voltage 5 V2 V1 VC MV1 MV2 0 3 to V3 Input voltage VIN 0 3 to VDD 0 3 Output voltage VO 0 3 to VDD 0 3 Operating temperature TOPR 40 to 90 C Storage temperature Bare chip TSTR 55 to 125 1 For the V3 V2 V1 VC MV1 and MV2 voltages be sure to satisfy the following conditions V3 V2 V1 VC MV1 MV2 VSSL VSSH 2 The use of IC exceeding the absolute maximum rating can cause permanent damage to the IC Du...

Page 57: ... f 1MHz 4 12 pF Oscillation frequency Built in oscillation fOSC Ta 25 C at maximum frequency 608 640 672 kHz 9 External input fCLO 160 References marked with an asterisk 1 The IC operations are not guaranteed when rapid voltage fluctuations are observed during access from MPU 2 For operating voltage range of VDI series and V3 series see Fig 9 4 3 A0 D0 to D7 SCL SI ___ RD E ___ WR R __ W ___ CS CL...

Page 58: ...4 gray scale fFR 80 Hz no n line inversion 1 13 bias non dispersion drive Table 9 2 Display all white Standard value 1 184 Duty 1 132 Duty VDD Booster magnification V3 voltage Typ Max Typ Max Unit Remarks 5V 20 125 210 112 190 µA 10 3V 20 110 185 100 170 Table 9 3 Display Heavy Load Pattern Standard value 1 184Duty 1 132 Duty VDD Booster magnification V3 voltage Typ Max Typ Max Unit Remarks 5V 20 ...

Page 59: ...with an asterisk 10 The built in oscillation circuit is used and 0 is written to all the bits of the display data RAM and displayed Current consumed by a single IC Current related to LCD panel capacity and wiring capacity is not included Applicable when no access is made from MPU 11 The built in oscillation circuit is used and display data that makes current consumption maximum is written and disp...

Page 60: ...rsion drive Ta 25 C VDD VDD2 5V V3 20V 0 50 100 150 200 100 120 140 160 180 Display Line I SS µA Display all white Display heavy load VDD VDD2 5V V3 20V Fig 9 1 VDD 5 0 V Display mode binary fFR 100 Hz no n line inversion 1 13 bias non dispersion drive Ta 25 C VDD V DD2 5V V3 20V 0 50 100 150 200 250 300 100 120 140 160 180 Display Line I SS µA Displayallwhite Display heavy load VDD V DD2 5V V3 20...

Page 61: ...eavy load pattern is written in fCYC VDD 5V V3 25V fFR 100 Hz no n line inversion built in power supply OFF 1 13 bias non dispersion drive display ON Ta 25 C 0 1 1 10 0 001 0 01 0 1 1 10 ｆCYC MHｚ I SS mA Fig 9 3 9 3 3 Operating Voltage Rage of VDI Series and V3 Series 3 0 5 5 VDD V 15 20 25 10 5 0 Operation voltage range of VDD and V3 V 3 V Fig 9 4 ...

Page 62: ...7 Item Display clock frequency fCL Frame frequency fFR Built in oscillation circuit is used See command 21 Built in oscillation circuit is not used External input fCL l 2 f f CL FR 2 CL clock correspond to 1 common line scanned period Frame frequency indicates the frequency that rewrites 1 frame but it does not indicate a signal a cycle of AC drive from the FR pin ...

Page 63: ...e it should be noted that current path and capacity must not be provided between the SVD2 and VDD VDI VDD2 13 The curve of the sensor analog output voltage SVD2 is approximated by the following expression 281 1 10 763 4 10 641 2 3 2 6 2 V T T VSVD Expression 9 1 The accuracy is 5 C at 40 to 90 C 14 It is temperature gradient of VSVD2 output approximation strait line Accuracy of analog sensor outpu...

Page 64: ... CHARACTERISTICS 10 1 System Bus Read Write Characteristics 1 80 Series MPU tCCLR tCCLW tCCHR tWCYC8 tWCYC8C tRCYC8 tRCYC8C tAW8 tAH8 tDS8 tDH8 tDH8C tACC8 tOH8 A0 D0 to D7 Write D0 to D7 Read ___ CS ___ WR ___ RD ___ CS ___ WR ___ RD 1 2 tf 3 tr 3 tCCLRC tCCLWC tCCHRC tCCHWC 4 Fig 10 1 ...

Page 65: ...pulse width ___ WR ___ WR tCCHW 350 Control H pulse width ___ CS ___ CS tCCHWC 600 Control H pulse width ___ RD ___ RD tCCHR 600 Control H pulse width ___ CS ___ CS tCCHRC 600 Data setup time D0 to D7 tDS8 600 Data hold time ___ WR tDH8 30 Data hold time ___ CS tDH8C 100 ___ RD access time tACC8 Cload 100pF 1000 Output disable time tOH8 50 600 1 Accessed by ___ WR and ___ RD at ___ CS LOW 2 Access...

Page 66: ...61 10 2 System Bus Read Write Characteristics 2 68 Series MPU tAW6 tAH6 A0 R __ W tWCYC6 tWCYC6C tRCYC6 tRCYC6C ___ CS tEWHR tEWHW tEWLR tEWLW E tDS6 tDH6 tDH6C tACC6 tACC6C tOH6 tOH6C D0 to D7 Write D0 to D7 Read ___ CS E 1 2 tf 3 tr 3 tEWHRC tEWHWC tEWLRC tEWLWC 4 Fig 10 2 ...

Page 67: ...C6 Cload 100pF 600 tACC6C 1000 Output disable time tOH6 100 1000 tOH6C 50 600 Enable H pulse width Read E tEWHR 600 Read ___ CS tEWHRC 1000 Write E tEWHW 600 Write ___ CS tEWHWC 1000 Enable L pulse width Read E tEWLR 1000 Read ___ CS tEWLRC 600 Write E tEWLW 1000 Write ___ CS tEWLWC 600 1 Accessed by E at ___ CS LOW 2 Accessed by ___ CS at E HIGH 3 The rising and trailing times tr and tf of the in...

Page 68: ...k cycle Write SCL tSCYC WR 250 ns Read tSCYC RD 450 SCL HIGH pulse width Write tSHW WR 50 Read tSHW RD 250 SCL LOW pulse width Write tSLW WR 150 Read tSLW RD 150 Address setup time Write A0 tSAS WR 50 Read tSAS RD 50 Address hold time Write tSAH WR 50 Read tSAH RD 50 Data setup time SI tSDS 50 Data hold time Write tSDH 50 ___ CS SCL time ___ CS tCSS 50 tCSH 150 ___ RD access time SI tACCS Cloud 10...

Page 69: ... delay time SYNC tDSYNC 0 500 Table 10 5 Input Timing VDD 3 0V to 5 5V Ta 40 to 90 C Standard value Item Signal Symbol Conditions Min Typ Max Unit FR delay time FR tDFR 1 25 1 25 µs F1 and F2 delay time F1 F2 tDF1 F2 1 25 1 25 µs SYNC delay time SYNC tDSYNC 1 25 1 25 µs Input clock duty ratio 2 tCLD 20 80 Input clock cycle tCLF 6 25 µs Input clock rise time 20 to 80 3 tr 15 ns Input clock fall tim...

Page 70: ...em Signal Symbol Conditions Min Typ Max Unit MPU access cycle WR ______ or RD _____ 80 series MPU Enable 68 series MPU SCL Serial interface fSACC 0 Hz Sampling setup time SVD2 tSSVD2 100 ms Sampling hold time SVD2 tHSVD2 0 ms 1 Stop an access from MPU for 80 series MPU input from the WR ______ or RD _____ pin for 68 series MPU input from the Enable pin and for the serial interface input from the S...

Page 71: ... REFERENCE EXAMPLE 66 EPSON S1D15722D01B000 Technical Manual Rev 1 1 11 POWER CIRCUIT REFERENCE EXAMPLE VDD 3 0V VDIS H S1D15722 V3 V2 V1 VC MV1 MV2 VSSH VDD VSSL VDD2 VDI VDIS VDD External power circuit VSSH Fig 11 1 ...

Page 72: ... by the pin each input pin should be controlled successfully 1 80 series MPU VSS VDD VCC GND D0 to D7 A1 to A7 A0 VSS VDD MPU P S C86 A0 Decoder S1D15722 _____ IORQ ___ RD ___ WR ____ RES ______ RESET ___ CS VDD2 VDD2 D0 to D7 ___ RD ___ WR ____ RES Fig 11 1 80 Series 2 68 series MPU VSS VDD VCC GND D0 to D7 A1 to A15 A0 VSS VDD MPU P S C86 A0 Decoder S1D15722 VMA E ____ RES ______ RESET ___ CS VD...

Page 73: ...ystal display area Set both master and slave the same number of display line using the command VDD VSS VDD VDI CL FR DOF _______ F1 F2 SYNC V3 V2 V1 VC MV1 MV2 VDIS M S CLS M S CLS VDI CL FR DOF _______ F1 F2 SYNC V3 V2 V1 VC MV1 MV2 VDIS S1D15722 Master S1D15722 Slave VSS VDD External power circuit Fig 13 1 Connection between Master and Slave Set VDIS of master HIGH VDIS of slave Low to supply VD...

Page 74: ...ts COM S1D15722 Fig 14 1 Example of 1 Chip Drive 2 Example of 2 chip configuration synchronize synchronize A The display is enlarged crosswise by locating on the right and left sides synchronize SEG 448 184 Dots S1D15722 Master SEG S1D15722 Slave COM COM SEG S1D15722 Master COM COM SEG S1D15722 Slave COM COM 224 368 dots B The display is enlarged lengthwise by locating up and down The SEG wiring m...

Page 75: ...s table in this development specification refers to the relationship on a numbered line 3 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson When using semiconductor chips the following points should be noted Precautions in Handling the IC against the Light If semiconductor chips are exposed to the strong light their c...

Page 76: ...arrow direction at VDI pin from bi directional to one way P27 added In 6 8 Reset circuit add bit D4 at MLS driving select register P42 to 43 Added IIn 7 Command at 26 Select MLS drive command add bit P4 and the description P4 0 n line frame inversion overlap OFF P4 1 n line frame inversion overlap ON 2008 6 11 1 1 P45 Added In 7 2 Command table at 26 Select MLS Drive command add a bit P4 ...

Page 77: ...Kong Phone 852 2585 4600 FAX 852 2827 4346 Telex 65542 EPSCO HX EPSON CHINA CO LTD SHENZHEN BRANCH 12 F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen Phone 86 755 2699 3828 FAX 86 755 2699 3838 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 Phone 886 2 8786 6688 FAX 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapo...

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Epson S1D15722 Series, Technical Manual

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