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ETM26E-03

Application Manua

l

Real Time Clock Module

RX-8801SA/JE

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Summary of Contents for RX-8801JE

Page 1: ...ETM26E 03 Application Manual Real Time Clock Module RX 8801SA JE ...

Page 2: ...for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications that require extremely high reliability such as applications stated below it is required to obtain the permission from E...

Page 3: ...ixed cycle timer interrupt function 14 8 3 2 Related registers for function of time update interrupts 15 8 3 3 Fixed cycle timer interrupt interval example 16 8 3 4 Fixed cycle timer start timing 16 8 4 Time Update Interrupt Function 17 8 4 1 Time update interrupt function diagram 17 8 4 2 Related registers for time update interrupt functions 18 8 5 Alarm Interrupt Function 19 8 4 1 Diagram of ala...

Page 4: ...rview This module is an I 2 C bus interface compliant real time clock which includes a 32 768 kHz DTCXO In addition to providing a calendar year month date day hour minute second function and a clock counter function this module provides an abundance of other functions including an alarm function fixed cycle timer function time update interrupt function and 32 768 kHz output function The devices i...

Page 5: ...s the C MOS output pin with output control provided via the FOE pin When FOE H high level this pin outputs a 32 768 kHz signal When output is stopped the FOUT pin Hi Z high impedance FOE Input This is an input pin used to control the output mode of the FOUT pin When this pin s level is high the FOUT pin is in output mode When it is low output via the FOUT pin is stopped INT Output This pins is use...

Page 6: ...sation voltage VTEM Temperature compensation voltage 2 2 3 0 5 5 V Clock supply voltage VCLK 1 6 3 0 5 5 V Operating temperature TOPR No condensation 40 25 85 C 6 Frequency Characteristics GND 0 V Item Symbol Condition Rating Unit U A Ta 0 to 40 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 1 9 1 3 4 2 Frequency stability Δ f f U B Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V 3 8 3 5 0 4 10 6 Frequency vo...

Page 7: ...DD 3 V 0 72 1 85 μA Current consumption 9 IDD9 VDD 5 V 430 900 Current consumption 10 IDD10 fSCL 0 Hz INT VDD FOE GND FOUT output OFF High Z Compensation ON peak VDD 3 V 180 350 μA FOE pin 0 8 VDD VDD 0 3 High level input voltage VIH SCL and SDA pins 0 7 VDD 5 5 V FOE pin GND 0 3 0 2 VDD Low level input voltage VIL SCL and SDA pins GND 0 3 0 3 VDD V VOH1 VDD 5 V IOH 1 mA 4 5 5 0 VOH2 VDD 3 V IOH 1...

Page 8: ...CL H tHIGH 0 6 μs Rise time for SCL and SDA tr 0 3 μs Fall time for SCL and SDA tf 0 3 μs Allowable spike time on bus tSP 50 ns FOUT duty tW t 50 of VDD level 40 50 60 Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Caution Wh...

Page 9: ...T pin goes to low level to indicate that an event has occurred However when a fixed cycle timer interrupt event has been generated low level output from the INT pin occurs only when the value of the control register s UIE bit is 1 This INT status is automatically cleared INT status changes from low level to Hi Z 7 8 ms a fixed value after the interrupt occurs 4 Alarm interrupt function The alarm i...

Page 10: ...ET 1 2 3 F Control Register CSEL1 CSEL0 UIE TIE AIE RESET 3 Note When after the initial power up or when the result of read out the VLF bit is 1 initialize all registers before using the module Be sure to avoid entering incorrect date and time data as clock operations are not guaranteed when the data or time data is incorrect 1 During the initial power up the TEST bit is reset to 0 and the VLF bit...

Page 11: ...nt occurs an interrupt signal is not generated or is canceled INT status changes from low to Hi Z Write Read 1 When a time update interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When a time update interrupt event occurs low level output from the INT pin occurs only when the value of the control register s UIE bit is 1 This INT status is automatically cle...

Page 12: ...ia the INT pin use software to monitor the value of the UF TF and AF interrupt flags 4 RESET bit It also resets the RTC module s internal counter value when the value is less than one second Writing a 1 to this bit stops the counter operation and resets the RTC module s internal counter value when the value is less than one second If a STOP condition or repeated START condition I2 C is received wh...

Page 13: ... has occurred Once this flag bit s value is 1 its value is retained until a 0 is written to it For details see 8 5 Alarm Interrupt Function 4 VLF Voltage Low Flag bit This flag bit indicates the retained status of clock operations or internal data Its value changes from 0 to 1 when data loss occurs such as due to a supply voltage drop Once this flag bit s value is 1 its value is retained until a 0...

Page 14: ...ting a 1 to this bit specifies DAY as the comparison object for the alarm interrupt function Writing a 0 to this bit specifies WEEK as the comparison object for the alarm interrupt function 3 USEL Update Interrupt Select bit This bit is used to specify either second update or minute update as the update generation timing of the time update interrupt function USEL Data update interrupts Auto reset ...

Page 15: ...20 10 8 4 2 1 This minute counter counts from 00 to 01 02 and up to 59 minutes after which it starts again from 00 minutes 3 Hour counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 HOUR 20 10 8 4 2 1 This hour counter counts from 00 hours to 01 02 and up to 23 hours after which it starts again from 00 hours 8 2 7 Day counter Reg 3 Address Function bit 7 bit 6 bit 5 bit 4 bi...

Page 16: ...uary and up to 12 December then starts again at 01 January 3 Year counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6 Years Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 The year counter counts from 00 01 02 and up to 99 then starts again at 00 Any year that is a multiple of four 04 08 12 88 92 96 etc is handled as a leap year 8 2 9 Alarm registers Reg 8 A Address Function bit 7 bit 6 bit 5 b...

Page 17: ...xed cycle timer stops 1 1 2 001 h 000 h 3 4 5 1 6 7 7 7 8 9 1 When a 1 is written to the TE bit the fixed cycle timer countdown starts from the preset value 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 001h to 000h an interrupt event occurs After the interrupt event that occurs when the count value changes fro...

Page 18: ... to the source clock setting 2 When the source clock has been set to second update or minute update the timing of both countdown and interrupts is coordinated with the clock update timing 2 Fixed cycle Timer Control register Reg B to C This register is used to set the default preset value for the counter Any count value from 1 001 h to 4095 FFFh can be set The counter counts down based on the sour...

Page 19: ... 3 3 Fixed cycle timer interrupt interval example Source clock Timer Counter setting 4096 Hz TSEL1 0 0 0 64 Hz TSEL1 0 0 1 Second update TSEL1 0 1 0 Minute update TSEL1 0 1 1 0 1 244 14 μs 15 625 ms 1 s 1 min 2 488 28 μs 31 25 ms 2 s 2 min 41 10 010 ms 640 63 ms 41 s 41 min 205 50 049 ms 3 203 s 205 s 205 min 410 100 10 ms 6 406 s 410 s 410 min 2048 500 00 ms 32 000 s 2048 s 2048 min 4095 0 9998 s...

Page 20: ...eared to zero Operation in RTC i i Write operation 1 2 3 4 1 5 6 7 1 A time update interrupt event occurs when the internal clock s value matches either the second update time or the minute update time The USEL bit s specification determines whether it is the second update time or the minute update time that must be matched 2 When a time update interrupt event occurs the UF bit value becomes 1 3 W...

Page 21: ...0 to 1 when a time update interrupt event occurs When this flag bit 1 its value is retained until a 0 is written to it UF Data Description 0 The UF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the INT low output status to be cleared to Hi Z Write 1 This bit is invalid after a 1 has been written to it 0 Time update interrupt events are no...

Page 22: ...ime is used as the setting the alarm will not occur until the counter counts up to the current date time i e an alarm will occur next time not immediately 2 When a time update interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occ...

Page 23: ...used to specify either WEEK or DAY as the target for alarm interrupt events WADA Data Description 0 Sets WEEK as target of alarm function DAY setting is ignored Write Read 1 Sets DAY as target of alarm function WEEK setting is ignored 2 Alarm registers Reg 8 to A Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8 MIN Alarm AE 40 20 10 8 4 2 1 9 HOUR Alarm AE 20 10 8 4 2 1 WEEK Alar...

Page 24: ...he AIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L Write Read 1 When an alarm interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When an alarm interrupt event occurs low level output from the INT pin occurs only when the AIE bit value is 1 This value is retained not automatically cleared until the AF bit is clea...

Page 25: ...its slave address matches the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse 8 6 2 System configuration All ports connected to the I2 C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line via a pull up resistance Co...

Page 26: ... stopped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 0 95 seconds A RESTART condition may be sent between a START condition and STOP condition but even in such...

Page 27: ...pulse corresponding to the 8th bit of data on the SCL line the transmitter releases the SDA line and the receiver sets the SDA line to low acknowledge level SCL from Master SDA from transmitter sending side ACK signal 1 2 8 9 SDA from receiver receiving side Release SDA Low active After transmitting the ACK signal if the Master remains the receiver for transfer of the next byte the SDA is released...

Page 28: ...01 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers RX 8801 s slave address with the R W bit set to read mode 8 Check for ACK signal from RX 8801 from this point on the CPU is the receiver and the RX 8801 is the transmitter 9 Data from address specified at 4 above is output by the RX 8801 10 CPU transfers ACK signal to RX 8801 11 Repeat 9 ...

Page 29: ...K 0 V VDET Item Symbol Condition Min Typ Max Unit Power supply detection voltage 1 VDET 2 2 V Power supply detection voltage 2 VLOW 1 6 V Power supply drop time t F 2 μs V Initial power up time t R1 10 ms V 1 6V VDD 3 6V 5 μs V Clock maintenance power up time t R2 1 6V VDD 3 6V 15 μs V ...

Page 30: ...ode Note SDA SCL SLAVE ADRS 0110 010 Note It uses the secondary battery or a lithium battery When using the seconding battery the diode is not required When using the lithium battery the diode is required For detailed value on the resistance please consult a battery maker 8 9 When used as a clock source 32 kHz TCXO RX 8801 VDD T1 GND 0 1 μF FOUT INT SCL SDA FOE VDD 32 768kHz O E TEST T2 VDD ...

Page 31: ...1 27 1 27 6 7 62 0 7 Unit mm 10 1 0 2 5 0 7 4 0 2 14 8 7 1 1 27 1 2 0 05 Min 3 2 0 1 0 35 The cylinder of the crystal oscillator can be seen in this area front but it has no affect on the performance of the device 9 1 2 Marking layout RX 8801 SA SOP 14pin Logo Type Production lot R 8801 E A123B Contents displayed indicate the general markings and display but are not the standards for the fonts siz...

Page 32: ...nit mm 1 5 3 8 1 5 0 65 9 5 85 0 3 0 35 0 65 5 4 7 0 0 3 1 20 11 10 The cylinder of the liquid crystal oscillator can be seen in this area back and front but it has no affect on the performance of the device 9 2 2 Marking layout RX 8801 JE VSOJ 20pin Logo Type Production lot R 8801 E A123B Contents displayed indicate the general markings and display but are not the standards for the fonts sizes an...

Page 33: ...nce If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device Also check again if the mounting conditions are later changed See Fig 2 profile for our evaluation of Soldering...

Page 34: ... Beijing China 100005 Phone 86 10 8522 1199 Fax 86 10 8522 1120 http www epson com cn Shanghai Branch High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch 12 F Dawning Mansion 12 Keji South Road Hi Tech Park Shenzhen China Phone 86 755 26993828 Fax 86 755 26993838 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong kong...

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