dg_usb3.0_dev_ip_demo_instruction_en.doc
15 May 2015
Page 1
USB3D
USB3D
USB3D
USB3D----IP (USB3.0
IP (USB3.0
IP (USB3.0
IP (USB3.0----Device function IP) demo manual
Device function IP) demo manual
Device function IP) demo manual
Device function IP) demo manual
Rev 1.3E / 15 May, 2015
This document describes USB3D-IP (USB3.0 device function IP-Core) evaluation procedure using Altera
evaluation board (CycloneIV GX board, CycloneVE board, and ArriaV GX starter board) or Xilinx
evaluation board (SP605, ML605, KC705, and ZC706 board) and USB3.0 adapter board with evaluation
sof-file or bit-file
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1....
Evaluation Environment
Evaluation Environment
Evaluation Environment
Evaluation Environment
This demo design operates under following environment shown at Figure 1....
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Altera Environment
Altera Environment
Altera Environment
Altera Environment
For Altera USB3.0 Device-IP evaluation, user must arrange following environment.
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Altera evaluation board (Cyclone IV GX board in this example)
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USB3.0 adapter board from DesignGateway [Part# AB08-USB3HSMC]
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USB3.0 A to A cable attached with adapter board.
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Altera sof-file download tool (programmer) and NiosII console.
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Host PC with USB3.0 port. (PCIe extension USB3.0 host card is also available, however, such PCIe
extension host card is sensitive to analog characteristics such as error occurrence at some PCIe slot
position. And PCIe extension host card cannot provide enough transfer performance when PCIe
interface is 1-lane and not GEN2 but GEN1 speed because GEN1 1-lane PCIe I/F limits its
performance to 2.5Gbps=200Mbyte/s at maximum.)
Figure
Figure
Figure
Figure 1
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1: Altera demo environment for USB3D
: Altera demo environment for USB3D
: Altera demo environment for USB3D
: Altera demo environment for USB3D----IP evaluation
IP evaluation
IP evaluation
IP evaluation
(Notes) Evaluation sof-file has 1-hour time limit operation after FPGA configuration.
