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STK22C48

16 Kbit (2K x 8) AutoStore nvSRAM

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document Number: 001-51000 Rev. **

 Revised January 30, 2009

Features

25 ns and 45 ns access times

Hands off automatic STORE on power down with external 68 
µF capacitor

STORE to QuantumTrap™ nonvolatile elements is initiated by 
software, hardware, or AutoStore™ on power down

RECALL to SRAM initiated by software or power up

Unlimited Read, Write, and Recall cycles

1,000,000 STORE cycles to QuantumTrap

100 year data retention to QuantumTrap

Single 5V+10% operation 

Commercial and industrial temperatures

28-pin 300 mil and (330 mil) SOIC package

RoHS compliance

Functional Description

The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware STORE is initiated with
the HSB pin.

  

STORE/

RECALL

CONTROL

POWER

CONTROL

STATIC RAM

ARRAY

32 X 512

Quantum Trap

32 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT

 BUFFERS

OE

CE
WE

HSB

V

CC

V

CAP

A

0

A

1

A

2

A

3

A

4

A

10

A

5

A

6

A

7

A

8

A

9

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

Logic Block Diagram

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Summary of Contents for STK22C48

Page 1: ...ctional Description The Cypress STK22C48 is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to th...

Page 2: ...ring read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak inter...

Page 3: ...ed Write or before the end of an CE controlled Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tHZWE after WE goes LOW AutoStore Operation During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip t...

Page 4: ...cts data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations The low voltage condition is detected when VCC is less than VSWITCH If the STK22C48 is in a Write mode both CE and WE are low at power up after a RECALL or after a STORE the Write is inhibited until a negative transition on CE or WE is detected This protects against inadvertent ...

Page 5: ... so on must always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system manufacturing test to ensure these system routines work consistently Power up boot firmware routines should rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the ...

Page 6: ...cle rate Values obtained without output loads 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs Do Not Care VCC Max Average current for duration tSTORE 2 mA ISB1 4 Average Vcc Current Standby Cycling TTL Input Levels tRC 25 ns CE VIH tRC 45 ns CE VIH Commercial 25 18 mA mA Industrial 26 19 mA mA ISB2 4 VCC Standby Current CE VCC 0 2V All others VIN 0 2V or VCC 0 2V Standby current ...

Page 7: ...nditions 28 SOIC 300 mil 28 SOIC 330 mil Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 TBD TBD C W ΘJC Thermal Resistance Junction to Case TBD TBD C W Figure 6 AC Test Loads AC Test Conditions 5 0V Output 30 pF R1 963Ω R2 512Ω 5 0V Output 5 pF R1 963Ω R2 512Ω For Tri state Specs Input Pulse...

Page 8: ...5 5 ns tHZCE 8 tEHQZ Chip Disable to Output Inactive 10 15 ns tLZOE 8 tGLQX Output Enable to Output Active 0 0 ns tHZOE 8 tGHQZ Output Disable to Output Inactive 10 15 ns tPU 5 tELICCH Chip Enable to Power Active 0 0 ns tPD 5 tEHICCL Chip Disable to Power Standby 25 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 6 7 Figure 8 SRAM Read Cycle 2 CE and OE Controlled 6 W5 W W2...

Page 9: ...s tHA tWHAX tEHAX Address Hold After End of Write 0 0 ns tHZWE 8 9 tWLQZ Write Enable to Output Disable 10 14 ns tLZWE 8 tWHQX Output Active After End of Write 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 10 11 Figure 10 SRAM Write Cycle 2 CE Controlled 10 11 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH IMPEDANCE PREVIOUS DATA...

Page 10: ...age Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V tVSBL 10 Low Voltage Trigger VSWITCH to HSB Low 300 ns Switching Waveform Figure 11 AutoStore Power Up RECALL WE Notes 12 tHRECALL starts from the time VCC rises above VSWITCH 13 CE and OE low for output behavior 14 CE and OE low and WE high for output behavior 15 HSB is asserted low for 1us when VCAP drops through VSWITCH If an SRAM...

Page 11: ...n STK22C48 Unit Min Max tDHSB 13 16 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tPHSB tHLHX Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform Figure 12 Hardware STORE Cycle Note 16 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 12: ...IC 300 mil Commercial STK22C48 NF45 51 85026 28 pin SOIC 300 mil STK22C48 SF45TR 51 85058 28 pin SOIC 330 mil STK22C48 SF45 51 85058 28 pin SOIC 330 mil STK22C48 NF45ITR 51 85026 28 pin SOIC 300 mil Industrial STK22C48 NF45I 51 85026 28 pin SOIC 300 mil STK22C48 SF45ITR 51 85058 28 pin SOIC 330 mil STK22C48 SF45I 51 85058 28 pin SOIC 330 mil All parts are Pb free The above table contains Final inf...

Page 13: ... 0125 3 17 0 015 0 38 0 050 1 27 0 013 0 33 0 019 0 48 0 026 0 66 0 032 0 81 0 697 17 70 0 713 18 11 0 004 0 10 1 14 15 28 PART S28 3 STANDARD PKG SZ28 3 LEAD FREE PKG MIN MAX NOTE 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 3 DIMENSIONS IN INCHES 4 PACKAGE WEIGHT 0 85gms DOES IN...

Page 14: ... as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITN...

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