Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 38-05610 Rev. *D
Revised November 6, 2008
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
■
High speed
❐
t
AA
= 10 ns
■
Low active power
❐
I
CC
= 175 mA at 10 ns
■
Low CMOS standby power
❐
I
SB2
= 25 mA
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE
1
, CE
2
, and CE
3
).
CE
1
controls the data on the I/O
0
– I/O
7
, while CE
2
controls the
data on I/O
8
– I/O
15
, and CE
3
controls the data on the data pins
I/O
16
– I/O
23
. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A
0
– A
18
). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O
0
– I/O
23
) are placed in a high impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For more infor-
mation, see the
Truth Table
on page 8.
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
512K x 24
ARRAY
I/O
0
– I/O
7
OE
I/O
8
– I/O
15
CE
1
, CE
2
, CE
3
WE
I/O
16
– I/O
23
CONTROL LOGIC
A
(9:0)
A
(18:10)
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