Avtron ADDvantage-32 Manual Download

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ADDvantage-32

ADVANCED CONTROL MODULE (ACM)

2008 Avtron Industrial Automation, Iuc.

Cleveland, Ohio

November 12,1993

Rev.

Aug

Summary of Contents for ADDvantage-32

Page 1: ...ADDvantage 32 ADVANCED CONTROL MODULE ACM I O 2008 Avtron Industrial Automation Iuc 1 Cleveland Ohio November 12 1993 Rev Aug 2 2010 ...

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Page 28: ...s 0 to 50 o C 32 to 122 o F 50 o C maximum surrounding air temperature rating Storage Temperature 20 to 55 o C 4 to 131 o F Relative Humidity 95 non condensing Operational Altitude 0 to 3 300 feet above sea level no derating required Above 3 300 feet derated linearly by 1 per 300 ft Additional Specifications are located in the supplemental drawing package A space heater may be necessary if condens...

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Page 61: ...T MARKER 4 14 4 12 BALANCE 4 16 4 13 BIT CONVERT 4 18 4 14 BIT INVERT 4 20 4 15 BIT SELECT 4 21 4 16 BUMPLESS SWITCH 4 22 4 17 CDS COUNTS DURING STOP 4 24 4 18 CLAMPING 4 26 4 19 COM LOSS 4 28 4 20 COM WD 4 29 4 21 COMPARATOR 4 30 4 22 COPY 4 31 4 23 CURRENT LIMIT 4 32 4 24 DEADBAND 4 36 4 25 DEMUX 4 37 4 26 DENSITY 4 38 4 27 DERIVATIVE GAIN D DT 4 40 4 28 DIFF TRIP 4 41 4 29 DIGITAL IN 4 43 4 30 ...

Page 62: ... AND INTEGRAL CONTROL PI 4 75 4 54 PROPORTIONAL AND INTEGRAL CONTROL WITH CASCADED HOLD BITS PI2 4 78 4 55 QUAD LTCH 4 81 4 56 RAMP 4 82 4 57 RATE CHANGE 4 84 4 58 RATIO 4 85 4 59 RECIPE 4 87 4 60 RESOLVER 1 4 89 4 61 RMP2 4 91 4 62 RRAMP3 4 99 4 63 SBXDIA 4 102 4 64 SBXDIA4 4 104 4 65 SDS SHEETS DURING STOP 4 107 4 66 SETPOINT 4 109 4 67 SNAPAVG 4 112 4 68 SPLICER 4 114 4 69 SUMMING JUNCTION SELE...

Page 63: ... inputs to the block performs its function and outputs the results The following control blocks are not used in all software applications They are a combination of all available control blocks Refer to Appendix A for software specific control block interconnections 4 1 2 AND This block implements a 2 input digital AND gate FI GURE 4 1 2 AND BLOCK 1 Inputs INPA Bit INPB Bit AND INPA INPB OUT 2 INPU...

Page 64: ...Control Block Description ADDvantage 32 4 2 2 Outputs OUT Bit 3 Implementation OUT is set to one if both INPA and INPB are equal to one OUT is set to a zero bit if either INPA or INPB is equal to zero ...

Page 65: ... ADDvantage 32 4 3 4 2 2 OR This block implements a 2 input digital OR gate FIGURE 4 2 2 OR BLOCK 1 Inputs INPA Bit INPB Bit 2 Outputs OUT Bit 3 Implementation OUT is set to one if either INPA or INPB is equal to one else OUT 0 ...

Page 66: ...sed to select one of four possible analog signal paths It can be used to control the application of multiple reference signals to a single input point FIGURE 4 3 4 ANALOG SELECT BLOCK 1 Inputs INPA Analog INPB Analog INPC Analog INPD Analog CNTL1 Bit CNTL2 Bit 2 Output OUT Analog ...

Page 67: ...lock Description ADDvantage 32 4 5 3 Implementation One of the input signals will be directed to the block output by the following combinations of control bits CNTL1 CNTL2 OUT 0 0 INPA 1 0 INPC 0 1 INPB 1 1 INPD ...

Page 68: ...ut digital AND gate AND INPE OUT 5 INPUT LOGICAL AND INPD INPC INPB INPA 5ANDD101 FIGURE 4 4 5 AND BLOCK 1 Inputs INPA Bit INPB Bit INPC Bit INPD Bit INPE Bit 2 Outputs OUT Bit 3 Implementation OUT 1 if INPA INPB INPC INPD and INPE are equal to one OUT 0 if any input is equal to zero ...

Page 69: ...he selection of which inputs are to be summed is set using a series of digital bits INPA INPB INPC INPD INPE A B C D E A B C D E OUT BIT1 BIT2 BIT3 BIT4 BIT5 5SUMMER FIGURE 4 5 FIVE SUMMER BLOCK 1 Inputs INPA Analog INPB Analog INPC Analog INPD Analog INPE Analog BIT1 Bit BIT2 Bit BIT3 Bit BIT4 Bit BIT5 Bit 2 Output OUT Analog ...

Page 70: ...Control Block Description ADDvantage 32 4 8 3 Implementation OUT INPA BIT1 INPB BIT2 INPC BIT3 INPD BIT4 INPE BIT5 If all 5 bits are low then OUT 0 ...

Page 71: ...inverts them FIGURE 4 6 8 BIT INVERT BLOCK 1 Inputs INP Digital 2 Outputs OUT Digital 3 Implementation If INP is high 1 then OUT will be low 0 If INP is low 0 then OUT will be high 1 The same occurs for the next seven input bits They are outputted to the next seven output addresses OUT INP INP 1 OUT 1 INP 7 OUT 7 8BITINVD101 ...

Page 72: ...s the absolute value of an analog variable The state of EN BIT determines if the OUT value equals INP or the absolute value of the INP value FIGURE 4 7 ABSOLUTE VALUE BLOCK 1 Inputs INP Analog EN Bit 2 Output OUT Analog 3 Implementation If EN is low then OUT INP If EN is high then OUT the absolute value of INP ...

Page 73: ...32 4 11 4 8 ANALOG INVERT The Invert block is used to invert the value of an analog signal FIGURE 4 8 ANALOG INVERT BLOCK 1 Inputs INP Analog EN Bit 2 Outputs OUT Analog 3 Implementation If EN is low then OUT INP If EN is high then OUT INP ...

Page 74: ... example switching from field current reference to field economy reference INPA INPB OUT ANALOG SELECT ANLOGSELLAN FIGURE 4 9 ANALOG SELECT BLOCK 1 Inputs INPA Analog INPB Analog SELA Bit 2 Outputs OUT Analog 3 Implementation If SELA bit is high set at 1 the OUTPUT is equal to INPA If SELA bit is low set at 0 the OUTPUT is equal to INPB ...

Page 75: ...to switch in references to control the passage of an analog value or signal between control blocks FIGURE 4 10 ANALOG SWITCH BLOCK 1 Inputs INP Analog EN Bit 2 Outputs OUT Analog 3 Implementation If the EN bit is high then OUT is equal to INP If the EN bit is low OUT is equal to zero ...

Page 76: ... the setpoint Therefore every nth sheet sets the output bit high The output bit remains high for the number of sheets entered in calibration as MARK HOLD then the bit goes low The internal counter resets when the MARK RESET bit is high FIGURE 4 11 ASM AUTO SHEET MARKER BLOCK 1 Inputs NUMBER SHTS Analog MARK STPT Analog MARK HOLD Analog MARK RESET Bit LOW HIGH MARK HOLD HOLD MARK AUTO MARK BIT MARK...

Page 77: ...iption ADDvantage 32 4 15 2 Outputs AUTO MARK Bit 3 Implementation If NUMBER SHTS MARK STPT then AUTO MARK goes high If NUMBER SHTS MARK STPT MARK HOLD then AUTO MARK goes low and n n 1 If MARK RESET bit is high then n 1 ...

Page 78: ...rating reference FIG URE 4 12 BALANCE BLOCK 1 Inputs REF Analog FDBK Analog BAL Bit RET Bit 2 Outputs OUT Analog DIF Analog 3 Implementation On a falling edge of the BAL input DIF will be sampled as REF FDBK DIF will not change until the next falling edge of the BAL input When the BAL input is low OUT REF DIF BAL FDBK REF TIME MAGNITUDE BALANCE OUTPUT ...

Page 79: ...ock On powerup of the ADDvantage 32 err 0 Retentive Block On powerup of the ADDvantage 32 DIF will be initialized under the following conditions If RET 0 DIF 0 If RET 1 DIF is set to its last value DIF must also be configured to a retentive point Y RET SETPT to be updated automatically on powerup ...

Page 80: ... This block can also be used as the X_IN value of a Table block enabling 16 separate setpoints FIGURE 4 13 BIT CONVERT BLOCK 1 Inputs INPA Bit INPB Bit INPC Bit INPD Bit ENABLE Bit 2 Outputs OUT Analog 3 Implementation OUT latches only when the ENABLE input is low OUT defaults to 0 on powerup When the ENABLE bit is high refer to the following table to determine the value of OUT ...

Page 81: ... 32 4 19 TABLE 4 13 Bit Convert Block OUT Values INPA INPB INPC INPD OUT 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 10 1 1 0 1 11 0 0 1 1 12 1 0 1 1 13 0 1 1 1 14 1 1 1 1 15 ...

Page 82: ...ck is used to provide an output bit which is always the opposite state of the blocks input bit INP OUT BIT INVERT BITINVRT FIGURE 4 14 BIT INVERT BLOCK 1 Inputs INP Bit 2 Outputs OUT Bit 3 Implementation If INP bit is high OUT bit is set low If INP bit is low OUT bit is set high ...

Page 83: ... block is used to select one of two different bit signal paths FIGURE 4 15 BIT SELECT BLOCK 1 Inputs INPA Bit INPB Bit SEL A Bit 2 Outputs OUT Analog 3 Implementation If SEL A bit is high set at 1 OUT is equal to INPA If SEL A bit is low set at 0 OUT is equal to INPB ...

Page 84: ...ock is used to provide a smooth BUMPLESS transition when switching control reference or feedback between two analog signals RAT1 RAT2 OUT REF1 REF2 SW DN1 DN2 BUMPSWLAN FIGURE 4 16 BUMPLESS SWITCH BLOCK 1 Inputs REF1 Analog REF2 Analog RAT1 Analog RAT2 Analog SW Bit HOLD Bit ...

Page 85: ...en REF1 REF2 polarity switches from the starting polarity When this condition occurs the DN1 bit goes high and the OUT follows REF1 without ramping When SW goes low the OUT ramps from REF1 to REF2 in the same manner as previously described When OUT equals REF2 the DN2 bit goes high and the OUT follows REF2 without ramping When the HOLD bit goes high the OUT freezes at the current value When deacti...

Page 86: ...counted during a controlled stop It is used in turret applications to determine when the drive run should be removed so that the turret will stop at the appropriate index position FIGURE 4 17 CDS COUNTS DURING STOP BLOCK 1 Inputs CDS REF Analog STOP RT Analog CDS ADJ Analog GEAR RATIO Analog PPR Analog 2 Outputs COUNT STOP Analog ...

Page 87: ...ADDvantage 32 4 25 3 Implementation ADJ CDS RT STOPPING PPR GR REF CDS PPR GR ADJ CDS RT STOPPING REF CDS CDS 2 2 Where CDS REF REFERENCE IN RPM STOPPING RT RATE IN RPM SEC CDS ADJ 2 60 SEC MIN GEAR RATIO NO UNITS PPR PULSES REV ...

Page 88: ...G A Clamping block is used to restrict an analog signal to a value between user selectable high MAXL and low MINL limits MAXL MINL MAX MIN CLAMPINGLAN FIGURE 4 18 CLAMPING BLOCK 1 Inputs INP Analog MAXL Analog MINL Analog 2 Outputs OUT Analog MAX Bit MIN Bit ...

Page 89: ...Control Block Description ADDvantage 32 4 27 3 Implementation If INP MAXL then OUT MAXL MAX high MIN low If INP MINL then OUT MINL MIN high MAX low If MINL INP MAXL then OUT INP MAX low MIN low ...

Page 90: ...lock Description ADDvantage 32 4 28 4 19 COM LOSS The Com Loss block is used as a communication watchdog TIM WDIN EN COM_LOSSLAN FIGURE 4 19 COM LOSS 1 Inputs TIM Bit EN Bit WDIN Bit 2 Outputs WDOUT Bit TRIP Bit ...

Page 91: ...tors the WDIN input and will set the TRIP output if the input fails to toggle transition from low to high or transition from high to low within the time period seconds defined by the TOUT input The WD OUT bit equates to the bit inverted state of the WDIN input The TRIP output will be reset to a logic level low Zero Bit when the EN input is set to a logic level low signal or if the WDIN begins to t...

Page 92: ...n a setpoint The HYS input sets up hysteresis to debounce the output bit OUT HYS HYS COMPARTRLAN FIGURE 4 21 COMPARATOR BLOCK 1 Inputs INP Analog INP Analog HYS Analog 2 Outputs OUT Bit 3 Implementation If INP increases so INP HYS INP then the OUT bit will go high If INP decreases so INP HYS _ INP then the OUT bit will go low ...

Page 93: ...Dvantage 32 4 31 4 22 COPY The Copy block takes the analog value at the input and copies the value to the output INP OUT COPYD101 COPY BLOCK FIGURE 4 22 COPY BLOCK 1 Inputs INP Analog 2 Outputs OUT Analog 3 Implementation OUT INP ...

Page 94: ...otor armature current rises above 110 motor nameplate IIR INTEGR will count up from zero when current is rising and count down when current falls below 110 The IIR INTEGR is used to calculate motor temperature The rate at which IIR INTEGR counts is determined by the magnitude of armature current above 100 and the thermal TC value The current limit taper feature can be disabled by setting P BYPASS ...

Page 95: ...igure 4 21 The POS I LIMIT and NEG I LIMIT outputs are usually configured to the MAXL and MINL inputs on the speed loop PI Control block Non Tapered Current Limits If non tapered current limits are desired the BY I2R input must be high by configuring P BYPASS I2R ONE BIT The current limit block constantly monitors the I2R Trip input A IIR INTEGR to detect when the motor armature current rises abov...

Page 96: ...thin the block to check the current limits by the SFDBK input A ABS ACT SPD When SFDBK BRK SPD the speed table output will equal START PER S IF SFDBK MAX SPD the speed table output will equal END PER S where the user should enter a value of 100 or less When SFDBK is between BRK SPD and MAX SPD the speed table output will equal the interpolation between START PER S and END PER S The POS LIM and NEG...

Page 97: ...100 Y MSPD BSPD X ST PERS END PER END PER S START PER S BREAK SPD MAX SPD LEAST WIN SELECT ANALOG OUT SEL A WIN LEAST OUT OUT INP INV INVERT SEL A OUT ANALOG SELECT 1 0 NEG I INPA INPB BY I2R INPA INPB INPA INPB INPB INPA BLOCK NEG NEG LIM I2R TRIP SFDBK POS I INPA INPB INPA INPB BY I2R INPA INPB INPA INPB BLOCK POS CURLIMITLAN FIGURE 4 23 CURRENT LIMIT BLOCK DIAGRAM ...

Page 98: ... A Deadband block is used to reset an analog signal to zero when it is less than a user selected value OUT DBAND DBAND FIGURE 4 24 DEADBAND BLOCK 1 Inputs REF Analog DBAND Analog 2 Outputs OUT Analog 3 Implementation If DBAND REF DBAND then OUT 0 else OUT REF ...

Page 99: ...ion The output bits are set as follows If BIT1 0 and BIT2 0 and INP 1 then OUT0 1 else OUT0 0 If BIT1 1 and BIT2 0 and INP 1 then OUT1 1 else OUT1 0 If BIT1 0 and BIT2 1 and INP 1 then OUT2 1 else OUT2 0 If BIT1 1 and BIT2 1 and INP 1 then OUT3 1 else OUT3 0 BIT1 DEMUX OUT 0 OUT 1 BIT2 OUT 2 OUT 3 INP 0 0 DEMUX 1 0 0 1 1 1 EN FIGURE 4 25 DEMUX BLOCK ...

Page 100: ...l of product It calculates the density of a roll over specific diameter ranges The range needs to be large enough to make the calculation accurately taking into account error in the diameter measurements FIGURE 4 26 DENSITY BLOCK 1 Inputs CNT Analog PPR Analog DIA Analog WRAPS Analog WGHT Analog RES Bit 2 Outputs DENSITY Analog AVG DIA Analog ...

Page 101: ... change until the number of winder revolutions equals WRAPS 1 winder revolution PPR amount of change in the CNT value When this occurs the following calculations are done DIA DIA at start of wraps count thick DIA DIA 2 WRAPS DEN WGHT thick ADIA DIA DIA 2 The outputs do not change until the next time the number of winder evolutions equals WRAPS or a RES occurs ...

Page 102: ... for inertia compensation FIGURE 4 27 DERIVATIVE GAIN BLOCK 1 Inputs INP Analog GAIN Analog LP Analog 2 Outputs OUT Analog 3 Implementation INP goes through a third order low pass filter with time constant LP in seconds This filters amplification of high frequency bounce OUT Rate of change of filtered INP GAIN TIME GAIN OUT INP DGAINDDT ...

Page 103: ...is used to detect alarm or fault conditions FIGURE 4 28 DIFF TRIP BLOCK 1 Inputs INPA Analog INPB Analog TICS Analog LMT Analog 2 Outputs OUT Analog TRP Bit 3 Implementation OUT is equal to INPA INPB If the absolute value of OUT is greater than LMT then the internal timer will start to count up each time the block is executed ...

Page 104: ...y high as long as the absolute value of OUT is greater than LMT As soon as the limit condition goes false the timer is reset to zero and the TRP output goes low NOTE The amount of time associated with a block execution can vary depending on the application Look up the TICS input label in Appendix C of the manual for the timing ...

Page 105: ...ge 32 4 43 4 29 DIGITAL IN The Digital Input block enables the eight digital inputs USER 7 through USER 14 from the optional FAX 32 board to be mapped to eight consecutive digital data table board addresses FIGURE 4 29 DIGITAL IN BLOCK ...

Page 106: ...Outputs START BIT 3 Implementation The digital input for USER 7 through USER 14 will equal ONE ON when the input s corresponding FAX 32 J2 terminal is switched to 24 VDC The digital input for USER 7 through USER 14 will equal ZERO OFF when the input s corresponding FAX 32 J2 terminal is switched to 0 VDC ...

Page 107: ...nts a 4 input digital OR OUT INPA INPB INPC INPD OR 4 INPUT LOGICAL OR DIGITOR FIGURE 4 30 DIGITAL OR BLOCK 1 Inputs INPA Bit INPB Bit INPC Bit INPD Bit 2 Outputs OUT Bit 3 Implementation OUT is set to one if either INPA INPB INPC or INPD is equal to one otherwise OUT equals zero ...

Page 108: ...k is used to divide two numbers The block checks for divide by zero to avoid a fault A B DIV INPA INPB 0 INPB 0 INPB 0 OUT DIVIDE DIVIDELAN FIGURE 4 31 DIVIDE BLOCK 1 Inputs INPA Analog INPB Analog 2 Output OUT Analog 3 Implementation If INPB 0 then OUT 0 else INPB INPA OUT ...

Page 109: ...here it is in contact with another speed controlled section or anywhere a SOFT speed regulator is required FIGURE 4 32 DROOP BLOCK 1 Inputs CUR Analog STPT Analog GAIN Analog REF Analog ENABLE Bit 2 Outputs OUT Analog 3 Implementation If ENABLE bit low OUT REF If ENABLE bit high If STPT CUR STPT then OUT REF If STPT CUR then OUT STPT CUR GAIN REF If STPT CUR then OUT STPT CUR GAIN REF REF CUR STPT...

Page 110: ...ill remain low Zero Bit while there is at least one CSP message transfer occurring to the ESBX board within 5 seconds This bit will transition from low to high 5 seconds following the point where all CIP message transfers are terminated The bit will reset to a logic level low when CIP message transfers resume Refer to Appendix I for detailed information regarding the ESBX module interface to Allen...

Page 111: ...cit communication becomes inactive for a time period greater than the R P I time the implicit message was scheduled to occur The bit will reset to a logic level low when Implicit messaging resumes Refer to Appendix I for detailed information regarding the ESBX module interface to Allen Bradley Ethernet IP communications protocol ...

Page 112: ... 50 4 34 ERROR This block is used to generate an error signal such as speed error or current error A B INPA INPB OUT A B SUB ERRORD101 FIGURE 4 34 ERROR BLOCK 1 Inputs INPA Analog INPB Analog 2 Outputs OUT Analog 3 Implementation OUT INPA INPB ...

Page 113: ...e of the frequency output is from 200 to 20 200 Hz To use the frequency as bidirectional reference set the offset so 10 100 Hz equals zero then scale frequency from 20 200 to 200 The INP to the frequency block is user configurable by P FREQUENCY FIGURE 4 35 FREQUENCY OUT BLOCK 1 Inputs INP Analog SPAN Analog OFF Analog 2 Outputs Not Applicable 3 Implementation The output frequency will be Frequenc...

Page 114: ...cription ADDvantage 32 4 52 4 36 GAIN The Gain block is used to scale and offset an analog signal FIGURE 4 36 GAIN BLOCK 1 Inputs INP Analog GAIN Analog OFF Analog 2 Outputs OUT Analog 3 Implementation OUT INP GAIN OFF ...

Page 115: ...f limits Corrective action can be taken at this point Overspeed and AT ZERO SPEED detection are implemented using a HI LOW Comparator The user can enable overspeed protection by configuring Y USR FAULT 2 OVER SPEED FIGURE 4 37 HI LO COMPARATOR BLOCK 1 Inputs HI Analog LOW Analog INP Analog HYS Analog STPT Analog 2 Outputs HI Bit LOW Bit ...

Page 116: ...INP increases so INP STPT HYS 100 _ STPT HI 100 HI bit goes high If INP decreases so INP STPT HYS 100 STPT HI 100 HI bit goes low If INP increases so INP STPT HYS 100 _ STPT LOW 100 LOW bit goes low If INP decreases so INP STPT HYS 100 STPT LOW 100 LOW bit goes high ...

Page 117: ...ternal error signal is equal to absolute value of INP minus the STPT input quantity times 0 1 If ZER is HIGH the error is equal to STPT 0 1 This error is fed into the integrator if the SQU input bit is low giving an IIT function If the SQU input is high then this error is squared the sign of signal is kept after the squaring before it goes into the integrator The integrator works the same as the P...

Page 118: ...Control Block Description ADDvantage 32 4 56 FIGURE 4 38 IIT BLOCK STPT IIT INP IGN X X X VAL WRN TRP 0 1 WST FST IRES SQU ZER I 0 1 ...

Page 119: ...f either latch LTCH1 or LTCH2 is high and either hold HLD1 or HLD2 is high then OUT goes high and stays high even if both latches later go low as long as hold stays high When either hold HLD1 or HLD2 is low then OUT goes low no matter what the state of the latch bits The hold inputs have a higher priority than the latch bits If the hold bits later go high the condition of OUT will be determined by...

Page 120: ...th latches later go low Upon transition of the latch bit high it does not matter what the state of the hold HLD1 or HLD2 is in determining the state of the OUT bit as it does in If Edge is low If OUT is high when either hold HLD1 or HLD2 transitions to low the OUT will go low It is important to note that the hold must be a transition not just the current state ...

Page 121: ...e of LEAD COMPENSATION is that it adds instability to the system by increasing high frequency closed loop gain LAG LEAD is added to a control loop to improve overshoot and relative stability The disadvantage of LAG COMPENSATION is that it results in a lower rise time FIGURE 4 40 LEAD LAG BLOCK 1 Inputs INP Analog LEAD Analog LAG Analog 2 Outputs OUT Analog ...

Page 122: ...ock Description ADDvantage 32 4 60 3 Implementation The LEAD LAG block is implemented to simulate the following equation H s LAG LEAD s LEAD s LAG Setting the LEAD value equal to LAG gives the block a unity gain ...

Page 123: ...ST WIN The block is used to select the lowest value of the inputs for a setpoint reference 1 Inputs INPA Analog INPB Analog INPC Analog 2 Outputs OUT Analog 3 Implementation OUT will equal the lowest input value e g If INPA 40 INPB 20 INPC 30 then OUT 30 ...

Page 124: ...BODE PLOT MAGNITUDE TIME C SECONDS 1 LOWPASS FIGURE 4 42 LOWPASS FILTER BLOCK 1 Inputs INP Analog TC Analog 2 Outputs OUT Analog 3 Implementation The lowpass filter takes the INP filters it for high frequency then outputs it to OUT The time constant in seconds for the filter is determined by TC Limits of the time constant are from 0 00277 to 2 5 seconds ...

Page 125: ...T WIN The block is used to select the highest value of the inputs for a setpoint reference 1 Inputs INPA Analog INPB Analog INPC Analog 2 Outputs OUT Analog 3 Implementation OUT will equal the highest input value e g If INPA 40 INPB 20 INPC 30 Then OUT 40 ...

Page 126: ...Dvantage 32 4 64 4 44 MOV8 This block is used to move eight variables to another location when enabled FIGURE 4 44 MOV8 BLOCK 1 Inputs IN1 Analog IN2 Analog IN3 Analog IN4 Analog IN5 Analog IN6 Analog IN7 Analog IN8 Analog EN Bit ...

Page 127: ... 32 4 65 2 Outputs OUT1 Analog 3 Implementation If EN is low the output does not change When EN is high OUT1 IN1 Next location IN2 Next location IN3 Next location IN4 Next location IN5 Next location IN6 Next location IN7 Next location IN8 ...

Page 128: ...IPLY This block is used to multiply two analog signals For example draw input speed reference signal FIGURE 4 45 MULTIPLY BLOCK 1 Inputs INPA Analog INPB Analog 2 Outputs OUT Analog 3 Implementation OUT INPA INPB A B INPA INP OU A X B MUL MULTIPLY MULTIPLY ...

Page 129: ... OUT fc 1 0 NOTCHFLLAN FIGURE 4 46 NOTCH FILTER BLOCK 1 Inputs INP Analog WD Analog DEPTH Analog FREQ Analog 2 Outputs OUT Analog 3 Implementation The DEPTH parameter sets the depth of the notch It can range from 0 to 100 Entering a number less than 2 will yield a notch depth of 0 A depth of 3 will reduce the gain by 1 3 33 at frequency point The FREQ parameter is used to set the center frequency ...

Page 130: ... 4 68 The WD parameter sets the width of the notch and is a unitless quantity ranging from 0 1 to 5 0 where 0 1 is the narrowest and 5 0 is the widest For example WD 2 will reach approximately 90 of the input at 2 Hz from the frequency point ...

Page 131: ...T Bit 3 Implementation If REF is high then OUT is high When REF goes low the block waits for TICS amount of block executions before OUT goes low If during the waiting REF goes back high the counter is reset NOTE The amount of time associated with a block execution can vary depending on the application Look up the TICS input label in Appendix C of the manual for the timing TICS REF OUT OFFTIM ...

Page 132: ...ts TICS Analog REF Bit 2 Outputs OUT Bit 3 Implementation If REF is low then OUT is low When REF goes high the block waits for TICS amount of block executions before OUT goes high If during the waiting REF goes back low the counter is reset FIGURE 4 48 ON TIMER BLOCK ...

Page 133: ...HOT BLOCK 1 Inputs INP Bit 2 Outputs OUT Bit 3 Implementation If INP is low then OUT is low When INP goes high OUT will go high for only one execution time NOTE The amount of time associated with a block execution can vary depending on the application Look up the input or output label in Appendix C of the manual for the timing ...

Page 134: ...g as the RES and HLD bits are low OUT the greater of Old OUT or INP Greatest wins if POS 1 OUT the least of Old OUT or INP Greatest wins if POS 0 If the HLD bit is high then OUT is held and INP is ignored If RES bit is high OUT 0 RES and HLD are both level triggered bits RES has higher priority than HLD On powerup OUT 0 FIGURE 4 50 PEAK DETECT BLOCK ...

Page 135: ...oint It can be used to detect a web loss condition on a center driven winder application DIF REF FDBK REF 100 PER DIF 0 1 PER DIF 0 FDBK REF A B A B 1 COMPARE DIF TRIP STPT PERDIFD101 FIGURE 4 51 PERCENT DIFFERENCE BLOCK 1 Inputs REF Analog FDBK Analog STPT Analog 2 Outputs DIF Analog TRIP Bit 3 Implementation DIF 1 FDBK REF 100 TRIP 1 when the ABSOLUTE DIF STPT else TRIP 0 If REF 0 then DIF 0 ...

Page 136: ...red using the keypad into actual values to be used in other blocks For example convert percent current limit into actual current limit A B MULT INP PER OUT A x B 100 DIV A x B A x B 100 PERCENT MULTIPLY PERMULT FIGURE 4 52 PERCENT MULTIPLY BLOCK 1 Inputs PER Analog INP Analog 2 Outputs OUT Analog 3 Implementation 100 INP PER OUT ...

Page 137: ...prevent the loop from overcompensating FIGURE 4 53 PI BLOCK 1 Inputs Data Type Description ERR Analog Input Signal P Analog Proportional Gain Value I Analog Integral Gain Value MAXL Analog Output High Limit Value MINL Analog Output Low Limit Value PREL Analog Integrator Preload Value HOLD Bit Integrator Hold Enable PRE Bit Integrator Preload Enable ERR ERR 0 MAX ERR 0 MIN P I PRE PREL IERR MINL MI...

Page 138: ...ss than 0 001 seconds then I is set to zero The sample time is used to convert to the block execution rate where typically Armature Current Loop 2 77 msec Speed Loop 8 msec Tension Loop 16 msec If OUT MAXL The following sequence of events will occur The MAX bit 1 HIGH The Proportional Error is set so OUT will not exceed MAXL If the Proportional Error 0 the Integral Error will start to increase to ...

Page 139: ...D input goes low The integrator hold input is used to hold the output value during major process disturbances If PRE HIGH then The Integral Error component is set to the PREL value and the Proportional Error component is set to zero so that OUT IERR PREL The IERR output is equal to the integrator component and can be used for diagnostic purposes ...

Page 140: ...ts to hold the integrator in either the positive or negative direction only FIGURE 4 54 PI2 BLOCK 1 Inputs Data Type Description ERR Analog Input Signal P Analog Proportional Gain Value I Analog Integral Gain Value MAXL Analog Output High Limit Value MINL Analog Output Low Limit Value PREL Analog Integrator Preload Value H UP Bit Integrator Positive Hold Enable H DN Bit Integrator Negative Hold En...

Page 141: ... Old Integral Error Value Second Time Sample I ERR 1 I is entered in seconds If I is entered at less than 0 001 seconds then I is set to zero The sample time is used to convert to the block execution rate where typically Armature Current Loop 2 77 msec Speed Loop 8 msec Tension Loop 16 msec If OUT MAXL The following sequence of events will occur The MAX bit 1 HIGH The Proportional Error is set so ...

Page 142: ...onal Error is not affected by the H UP input If H DN HIGH and PRE LOW then The Integral Error component cannot increase in the negative direction until the H DN input goes low Negative ERR values are ignored by the integral error component The integrator hold down input is used to keep the integrator from increasing in the negative direction during major process disturbances Note that the Proporti...

Page 143: ...3 Implementation On a low to high transition of the EN input the following outputs are sampled If BIT1 1 then OUT1 1 else OUT1 0 If BIT2 1 then OUT2 1 else OUT2 0 If BIT3 1 then OUT3 1 else OUT3 0 If BIT4 1 then OUT4 1 else OUT4 0 If EN is low on power up then all outputs will equal 0 If EN is high on power up then sample the bits FIGURE 4 55 QUAD LTCH BLOCK ...

Page 144: ... block provides a variable rate linear ramp with user programmable smoothing The purpose of this block is to provide a smooth reference from changing setpoint values FIGURE 4 56 RAMP BLOCK 1 Inputs REF Analog UP Analog DWN Analog RND Analog RES Bit HLD Bit ZERO Bit ...

Page 145: ...ue while the HLD ZERO bits are set high and the RES bit is low If REF is increasing faster than UP the RMP bit is set high and OUT ramps at the UP value If UP is equal to zero then the OUT ramps with the REF If REF decreases faster than DWN the RAMP bit is set high and OUT ramps at the DWN value If DWN is equal to zero then the OUT ramps with the REF If neither of the preceding conditions are true...

Page 146: ... user programmable maximum rate limit OUTPUT RATE INPUT TIME MAGNITUDE INP OUT RATECHG FIGURE 4 57 RATE CHANGE BLOCK 1 Inputs INP Analog RATE Analog 2 Outputs OUT Analog 3 Implementation RATE is scaled in units second If INP is changing less than RATE OUT is equal to INP If INP is changing faster than RATE OUT changes at the RATE value ...

Page 147: ...nder or an unwinder The initial diameter is a preset input value to obtain the correct diameter starting speed FIGURE 4 58 RATIO BLOCK 1 Inputs IDIAM Analog TACH1 Analog TACH2 Analog GAIN Analog MAX Analog MIN Analog RT Analog HLD Bit MAX MIN GAIN IDIAM UP UP MAX MIN A B X C A B C TACH1 TACH2 HLD RT RES RES UP RES RES RES RES UN OUT BI OUT RATIO ...

Page 148: ...is high then UNOUT equals the highest BIOUT since the last reset If the UP bit is low then the UNOUT equals the lowest BIOUT since the last reset The RES bit is used to reset both BIOUT and UNOUT to the IDIAM value It stays at this value as long as the RES bit is high The RES bit has a higher priority than the HOLD bit Non retentive Block On powerup of the ADDvantage 32 UNOUT IDIAM BIOUT IDIAM Ret...

Page 149: ... the OUT locations 10 values are set to the RECA values When the EN bit is high the block will select which block of 10 values to output based on the ENA ENB and ENC bits ENA transfers RECA data ENB transfers RECB data ENC transfers RECC data When EN is low no transitions occur ENA has the highest priority and is also used when no enable is present ENB is the second highest priority On power up FL...

Page 150: ...Control Block Description ADDvantage 32 4 88 FIGURE 4 59 RECIPE BLOCK RECA RECIPE 1 FLT ENC ENB ENA ERR EN 2 9 1 RECB 9 2 1 RECC 9 2 9 2 1 OUT ...

Page 151: ...ver board The Resolver board mounts on the first SBX site on the Maxi system board It provides 16 digital inputs and two digital outputs This block provides the software interface to the board FIGURE 4 60 RESOLVER 1 BLOCK 1 Inputs SPAN Analog ZERO Analog DO 1 Digital DO 2 Digital CNT 1 Digital CNT 2 Digital 2 Outputs RES Analog D IN Digital ...

Page 152: ...d 0 0 4 bits 1 0 8 bits 0 1 12 bits 1 1 16 bits The number of bits determined by the above table is then converted to a BCD number and then scaled to the block s output value RES as follows BCD number SPAN ZERO RES EXAMPLE CNT 1 LOW CNT 2 HIGH INPUT BITS 0100 0101 0000 BCD VALUE 4 5 0 SPAN 2 OFF 100 RES 450 2 100 1 000 All 16 input bits are outputted as digital bits in consecutive order starting a...

Page 153: ...etween the RAMP block and RMP2 is the RND input RAMP uses a low pass filter for rounding causing a J curve The RMP2 implements a rate of change limit on the ramp causing a uniform S curve FIGURE 4 61 RMP2 BLOCK The RMP2 block can be divided internally into three components to aid in the understanding of its operation These components are a Ramp Change Block a Rate of Change Limit Block and Additio...

Page 154: ...GURE 4 61A RAMP CHANGE BLOCK 1 Inputs UP Analog DWN Analog REF Analog 2 Outputs RP OUT Analog RMP Bit 3 Implementation The following holds true while the HLD ZERO bits are set high and the RES bit is low explained in detail in ADDITIONAL CONTROL I O ...

Page 155: ...Ramp Output RND Analog 2 Outputs OUT Analog 3 Implementation The rate of change limit block ROC filter is internal to the RMP2 Control Block The purpose of this stage of the RMP2 block is to round the corners created by the ramp change block Figure 4 61B The ROC filter produces rounding by limiting the ramp rate of the input to the output over time The limiting occurs as a result of a calculated v...

Page 156: ... time dependent of the form Rate S T Equation 4 61 1 where S is the analog value RND units Sec 2 and T Sec is the point in time since the start of the ramp input The maximum rate of change of the filter output will not exceed that of the input over a long enough time interval As an example note on Figure 4 61B that the plot starts at time t 0 Sec The rate of change at the input of the filter block...

Page 157: ...e becomes zero The filter will now cause the output rate to decrease by 5 FPM SEC2 from its maximum value of 20FPM S while the input rate is zero thus Exact Time Maximum rate of change Slope 1 Sec 5 FPM SEC 2 Sec 10 FPM SEC 3 Sec 15 FPM SEC 4 Sec 20 FPM SEC 5 Sec 20 FPM SEC 6 Sec 15 FPM SEC 7 Sec 10 FPM SEC 8 Sec 5 FPM SEC 9 Sec 0 FPM SEC 10 Sec 0 FPM SEC To accurately select an appropriate value ...

Page 158: ... UP or DWN ramp rates in addition to the RND input If the RES bit is high OUT REF Second in priority If the HLD bit is low OUT is held at its present value The rounding continues to prevent a step response When HLD goes high OUT ramps to REF by the appropriate rate The following figures 4 61C 4 61D and 4 61E graphically represent various RMP2 Control block input results FIGURE 4 61C ...

Page 159: ...Control Block Description ADDvantage 32 4 97 FIGURE 4 61D ...

Page 160: ...Control Block Description ADDvantage 32 4 98 FIGURE 4 61E ...

Page 161: ... with user programmable smoothing The purpose of this block is to provide a smooth reference from changing setpoint values The difference between the RRAMP3 block and RMP2 is the additional RAMP inputs The RRAMP3 block has four ramp rates instead of two See below RRAMP3 RND AF DF AR DR FIGURE 4 62 RRAMP3 BLOCK ...

Page 162: ...he understanding of its operation These components are a Ramp Change Block a Rate of Change Limit Block and Additional Control I O as can be seen in Figure 4 62A FIGURE 4 62A INTERNAL CONTROL BLOCKS RAMP CHANGE BLOCK 1 Inputs REF Analog AF Analog DF Analog AR Analog DR Analog RND Analog RES Digital HLD Digital ZERO Digital ...

Page 163: ... Figure 4 61 If AF is equal to zero then the RP OUT ramps with REF If REF decreases but still positive faster than DF the RMP bit is set high and RP OUT ramps at the DF value time period t3 to t4 of Figure 4 62 If DF is equal to zero then the RP OUT ramps with REF If neither of the preceding conditions is true the RMP bit is set low and RP OUT equals REF AR and DR work the same as AF and DF but ar...

Page 164: ... pickup This block requires the GSBX board connected to the Maxi system board The board provides the following Reference pulse generator input 2 Once per revolution pickups 8 Definable digital inputs 4 Definable digital outputs FIGURE 4 63 SBXDIA BLOCK 1 Inputs IDIAM1 Analog IDIAM2 Analog CALD1 Analog CALD2 Analog RES1 Digital RES2 Digital HLD1 Digital HLD2 Digital ...

Page 165: ...ES2 HLD2 DIA2 CALD2 work on the same principles DO1 through DO4 are the programmable digital outputs available on the board These outputs must be isolated DI1 First location where the eight digital inputs are stored It will use the next seven locations to store the information 4 Application Note The GSBX board has the following hardware assignments for this block Pin 15 Reference Frequency Input P...

Page 166: ...kup This block requires the GSBX board connected to the Maxi system board The board provides the following Reference pulse generator input 4 Once per revolution pickups 8 Definable digital inputs 4 Definable digital outputs FIGURE 4 64 SBXDIA4 BLOCK 1 Inputs IDIAM1 Analog IDIAM2 Analog IDIAM3 Analog IDIAM4 Analog CALD1 Analog RATE1 Analog MAX DIA1 Analog MIN DIA1 Analog ...

Page 167: ...ach roll which record once per revolution CALD1 RATE1 MAX DIA1 MIN DIA1 and DIA1 all point to the first diameter s parameters The other three diameter parameters are in consecutive order If the RES1 is high then DIA1 IDIAM1 If HLD1 is high the output is frozen at its last value RES1 has a higher priority If RES1 and HLD1 are low then DIA1 is calculated as follows DIA1 Edges read since last pickup ...

Page 168: ...ments for this block Pin 15 Reference Frequency Input Pin 17 Pick up pulse 1 Pin 4 Pick up pulse 2 Pin 16 Pick up pulse 3 Pin 3 Pick up pulse 4 Pins 9 13 22 Common DIN1 Pin 21 DIN2 Pin 8 DIN3 Pin 20 DIN4 Pin 7 DIN5 Pin 19 DIN6 Pin 6 DIN7 Pin 18 DIN8 Pin 5 DOUT1 Pin 12 DOUT2 Pin 24 DOUT3 Pin 11 DOUT4 Pin 23 Additionally this block can be used to calculate values other than diameter To do this facto...

Page 169: ...ut during the stop When the selected number of sheets has been cut the line will automatically begin to ramp to a stop The line will stop after cutting the selected number of sheets A X B SDS SHEETS DURING STOP WEBS LNGTH B A RAT REF REF ADJ RAT WEBS LNGTH SDS ADJ 2 EN 0 SDSSHT1D101 FIGURE 4 65 SDS SHEETS DURING STOP BLOCK 1 Inputs REF Analog RAT Analog ADJ Analog WEBS Analog LNGTH Analog EN Digit...

Page 170: ...igh LNGTH ADJ RAT WEBS REF SDS 2 Where RAT line speed in units per second 10 UNITS SPEED LINE UNITS LENGTH CUT 60 2 ADJ Else SDS 0 60 60 seconds 1 minute to adjust stopping rate in seconds and line speed in minutes 2 the factor used to obtain the integral number of sheets during the ramped stop ...

Page 171: ...DEC are adjustable along with the limits The limits can be defined as min max difference or ratio draw This block is used in the beginning of the speed loop and tension loop FIGURE 4 66 SETPOINT BLOCK 1 Inputs REF Analog RES Bit INC Bit DEC Bit INCR Analog DECR Analog MAXL Analog MINL Analog ABS Bit UP Bit RET Bit INC DEC MAX RES MINL MAXL OUT REF SETPOINT REF OUT ...

Page 172: ...The DEC DECR and MIN operate in the same manner as the INC functions If the UP input is high and REF changes OUT will reset to equal REF and the INC DEC changes will be negated If the UP input is low and REF changes OUT changes depending on the ABS input If the ABS bit is low the OUT value changes by the REF value multiplied by the ratio of the INC DEC change Example ABS BIT LOW REF equals 100 and...

Page 173: ...he drive OUT will be initialized under the following conditions If RET 0 and ABS 0 then DIF 1 within limits If RET 0 and ABS 1 then DIF 0 within limits If RET 1 then DIF is not initialized If ABS 0 then OUT INP DIF If ABS 1 then OUT INP DIF If a retentive setpoint is desired configure a retentive point Y RET SETPT to DIF so it updates automatically upon powerup Configure the RES input to a zero bi...

Page 174: ...the internal Count2 and Sum2 is set equal to Outputs CNT and TTL Otherwise they are set equal to zero Also internal Count1 and Sum1 is set to zero on powerup All three outputs go to zero on powerup also When the RES bit is high then both counters and sums are set equal to zero When the hold bit is high both counters and sums are held at their current value If both RES and HLD are low then Every ti...

Page 175: ...Control Block Description ADDvantage 32 4 113 FIGURE 4 67 SNAPAVG BLOCK ...

Page 176: ... ON DIA GL A CL A SPD R PR F KN F SPLICER SPLICER FIGURE 4 68 SPLICER BLOCK 1 Inputs PR T Analog Pressure Roll Reaction Time Sec KN T Analog Knife Reaction Time Sec TAIL Analog Tail Length Inches GR Analog Gear Ratio for Oncoming Roll PPR Analog Tach PPR for Oncoming Roll LGTH Analog Static Length Inches ON DIA Analog Oncoming Roll Diameter Inches GL A Analog Glue Line Angle Degrees CL A Analog Cl...

Page 177: ... K RPS ANGLE RPS PR T 360º TMP GL A ANGLE If TMP 0 1 TMP TMP 360º Else TMP TMP CL A o 360 TMP K F PR Pressure Roll Firing Count TMP PR F TMP TMP PPS PR T TMP TMP K o 360 A CL 1 TMP TMP PPS KN T π DIA ON LGTH TAIL K 2 TMP TMP TMP TMP2 If TMP 0 TMP TMP K PR F PR F K Else KN F TMP Knife Firing Count ...

Page 178: ...ence and tension trim It selects which inputs to add using the bit select lines FIGURE 4 69 SUMMING BLOCK 1 Inputs INPA Analog INPB Analog INPC Analog BIT1 Bit BIT2 Bit BIT3 Bit 2 Outputs OUT Analog 3 Implementation OUT INPA BIT1 INPB BIT2 INPC BIT3 If all 3 bits are low then OUT 0 BIT1 BIT2 BIT3 A B C A B C INPA INPB INPC OUT SUMMING3 ...

Page 179: ...actor which is proportional to a second analog variable X IN An example of such an application would be to taper a tension setpoint based on roll diameter FIGURE 4 70 TABLE BLOCK 1 Inputs INP Analog X_IN Analog GAIN Analog TABLE 0 3 2 Outputs OUT Analog Y15 Y0 Y1 Y2 Y3 Y4 Y5 Y6 f X_IN X0 X1 X2 X3 X4 X5 X15 X6 X_IN TABLE ...

Page 180: ...array 2 16 in size of x y points where x values are entered in ascending order Refer to section 6 3 4 Tables Menu for additional explanation If X_IN is less than the first X value in the TABLE then f X_IN the first y0 value If X_IN is greater than the last X value in the TABLE then f X_IN the y15 point If X_IN equals an X value in the TABLE then f X_IN the y value associated with that X point If X...

Page 181: ...ibed below The difference between the two blocks is described in the SPECIAL NOTE SW2 TACH 1 FAIL SW1 TACH 2 FAIL SWC 1 OR 2 1 OR 2 1 OR 2 SWC SW2 1 OR 2 SW2 SWC SWC SW1 SW1 TACH 1 TACH 2 CEMF OUT SPDVOL SPDVOL SPDVOL 2WARN 1WARN 1WARN 2WARN RED RED RED RES TL VRED TL RED RED 1WARN 2WARN RES RES 1WARN 2WARN TACHSEL FIGURE 4 71 TACH SELECT AND TACH SELECT W BLOCK ...

Page 182: ...nalog CEMF Analog MXSPD Analog GAIN Analog SPDVOL Bit 1 OR 2 Bit V RED Bit RED Bit RES Bit 2 Outputs OUT Analog 1WARN Bit 2WARN Bit TL Bit 3 Implementation The speed output of the TACH SELECT block is selected from CEMF TACH1 or TACH2 inputs and scaled by the GAIN input In order to work properly the CEMF TACH1 and TACH2 inputs need to be properly scaled into the appropriate units If TACH feedback ...

Page 183: ... on if a TACH2 failure is detected the 2WARN bit is turned on If tach feedback is used SPDVOL high and if a tach failure is detected then the TACH SELECT block can be configured to automatically switch to the redundant tach or to control in CEMF The logic is described in Figure 4 68 and as follows If SPDVOL high and RED high then if a tach failure is detected the output will switch from the failed...

Page 184: ...CT block Any time a tach failure is detected the TACH SELECT block will set appropriate output bits and switch speed feedback as the logic requires The outputs will remain in their states until the RES turns on If the RES input is maintained in the high state the TACH SELECT block will not switch to any redundant modes and tach failures will not be detected SPECIAL NOTE The TACH SELECT block diffe...

Page 185: ...ntil an appropriate count has occurred It can be used to buffer faults for FIFO logging or to shut the drive down if in maximum tension for a period of time CNT REF RES HLD TIMERLAN FIGURE 4 72 TIMER BLOCK 1 Inputs HLD Bit RES Bit REF Bit RET Bit CNT Analog 1 1 000 000 2 Outputs SET Bit ZERO Bit VAL Analog ...

Page 186: ... occurs If REF 1 and VAL CNT then VAL VAL 1 If REF 0 and VAL 0 then VAL VAL 1 If VAL CNT then SET 1 else SET 0 When SET 1 it latches until a reset occurs Non retentive Block On powerup of the ADDvantage 32 VAL 0 Retentive Block On powerup of the ADDvantage 32 VAL will be initialized under the following conditions If RET 0 then VAL 0 If RET 1 VAL is set to its last value prior to power loss VAL mus...

Page 187: ...le revolutions This diameter calculation block can be used instead of the RATIO block It is as accurate as the value of THCK that is entered THCK is the average thickness of the material A B C MULT 2 ABC ADD SUB IDIAM 2 ABC IDIAM 2 ABC LNTH GAIN THCK IDIAM RES UP DWN RES TYPE2DIALAN FIGURE 4 73 TYPE 2 DIA BLOCK 1 Inputs THCK Analog IDIAM Analog LNTH Analog MAX Analog MIN Analog GAIN Analog UP DWN ...

Page 188: ... clamped at the limit When the RES bit is set low the DIA is calculated by the following If UP DWN is high then DIA LNTH GAIN 2 THCK IDIAM If UP DWN is low then DIA IDIAM LNTH GAIN 2 THCK Length needs to be configured to the frequency counter from the winder tach The counter needs to be reset at new roll Length divided by Gain should be equal to roll revolutions for the block to work properly ...

Page 189: ... footage of the surface roll section The accuracy of this block is comparable to the value of THICK DIA THICK is the average thickness of the material FIGURE 4 74 TYPE 3 DIA BLOCK 1 Inputs THICK Analog IDIAM Analog LENGTH Analog MAX DIA Analog MIN DIA Analog UP DWN Bit RESET Bit RET Bit 2 Outputs DIA Analog IN MAX Bit IN MIN Bit ...

Page 190: ...r an unwinder system set the UP DWN bit low DIA increases by 2X THICK each time the following equation is true LENGTH New π DIA Length Old NOTE LENGTH Footage value of material from tach counters THICK Average thickness of material Entered in process units Non retentive Block On powerup of the ADDvantage 32 DIA IDIAM Retentive Block On powerup of the ADDvantage 32 DIA will be initialized under the...

Page 191: ... block rescales the minimum and maximum limits of a given value to 0 1 FIGURE 4 75 UNITY SCALE BLOCK 1 Inputs INP Analog MIN Analog MAX Analog 2 Outputs OUT Analog 3 Implementation If MIN MAX 0 then OUT MIN INP MIN MAX If MIN MAX 0 then OUT 0 MIN INP MIN IN OUT MA MIN OU UNITYSCL ...

Page 192: ...is by disabling the regenerating bridge current limit in a low voltage condition FIGURE 4 76 UV PROTECT BLOCK 1 Inputs POSI Analog NEGI Analog VAC Analog LOW Analog CEMF Analog 2 Outputs POSO Analog NEGO Analog 3 Implementation If VAC is greater than the LOW input then POSO POSI and NEGO NEGI Otherwise a low line condition is present and the following occurs ...

Page 193: ...tion ADDvantage 32 4 131 If CEMF is Positive POSO POSI NEGO 0 1 If CEMF is Negative POSO 0 1 NEGO NEGI In the application execute the block between the current limit setpoints and the current loop limit to protect the drive ...

Page 194: ...onst width dia4 core dia4 Therefore total inertia of a roll of material is the result of the previous equation plus the fixed inertia FIGURE 4 77 WINDER WK D BLOCK 1 Inputs VAR Analog WID Analog DIA Analog FIX Analog CDIA Analog VDIA Analog 2 Outputs WK Analog 3 Implementation WK VDIA FIX CDIA DIA WID VAR 4 4 VAR x WID x DIA CDIA 4 4 FIX CDIA VAR WID DIA VDIA A B SUM A B DIA DIV A B WK A B DIA WIN...

Page 195: ...ue 2 For a Fixed Diameter Time FPM in Change WK Torque 2 For a Variable Diameter The D DT block is used for Time FPM in Change Therefore the amount of current needed to accelerate a roll should equal the output of the WK D block times the output of the D DT block This should be calculated for a core first DIA CDIA and then a full roll of material CDIA MAXIMUM DIAMETER ...

Page 196: ...ut and checks to see if it is between a high and low setpoint The block offers options for absolute value of the input and a complementary output bit HI LOW INP IN OUT WINCOMPD101 FIGURE 4 78 WINDOW COMPARE BLOCK 1 Inputs INP Analog HI Analog LOW Analog ABS Digital 2 Outputs IN Digital OUT Digital ...

Page 197: ...Control Block Description ADDvantage 32 4 135 3 Implementation If ABS is Low 0 then IN 1 if LOW INP HI Else IN 0 If ABS is High 1 then IN 1 if LOW INP HI Else IN 0 If IN 1 OUT 0 Else IN 0 OUT 1 ...

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Page 271: ... request 9 1 DATA TABLES Information in the ADDvantage 32 is accessed using tables Files Each table contains a specific group of parameters or information associated with those parameters For example one table contains the numerical data for all the C parameters while a second table contains the units for these parameters 9 2 DATA TABLE STRUCTURES Data tables for the ADDvantage 32 start at number ...

Page 272: ...ough writing to the EEPROM can occur thousands of times it is not recommended Table 9 1 contains the data files tables available in the ADDvantage 32 The items listed in Table 9 1 are defined as follows 1 File Number Number of the table containing the data 2 Table Name Name of the table containing the data 3 Structure Number of bytes required for one element of data in the table 4 Data Type Data f...

Page 273: ...RIVE CAL LABELS DRIVE CAL UNITS DRIVE CAL HIGH LIMITS DRIVE CAL LOW LIMITS DRIVE CAL DEFAULTS DRIVE CONFIG LABEL DRIVE CONFIG LEGALS DRIVE CONFIG DRIVE CAL SELECT LIST CHECK SUM CAL VERSION DRIVE SOFTWARE AND VERSION NUMBER TIME ARRAY ANALYZER CAL LABELS 4 11 6 6 6 4 4 4 4 11 4 4 4 2 11 6 2 6 4 2 11 11 6 4 4 4 11 2 2 4 11 4 2 2 4 11 FP A A A A FP FP FP FP A FP FP FP I A A I A FP I A A A FP FP FP A...

Page 274: ...IAG TRACE DATA CHAN 3 DIAG TRACE DATA CHAN 4 RETURN FAULTS KEYBOARD DISPLAY MODE VIRTUAL KEYBOARD DISPLAY DOWNLOADING RETURN FAULTS ARM TRACE TRACE FTRACE LINK CONTROL BITS 2 2 2 2 2 2 4 4 4 4 2 2 1 2 2 2 2 2 2 I I I I I I FP FP FP FP I I A I I I I I I RO R W RO RO RO RO RO RO RO RO RO R W R W R W R W R W RO RO R W N A Z007 Z0 Z107 Z1 Z207 Z2 Z307 Z3 N A N A N A N A N A N A N A N A N A N A N A N A...

Page 275: ...lay Sending a write message for this table and the first element of 20H 20H 59H 50H 4DH 20H Y P M would modify the display units to be YPM instead of FPM 9 3 4 FILE 12 DEFAULT ADT UNITS This file contains the default units for the corresponding analog input elements 9 3 5 FILE 13 CAL TABLE UNITS This file contains all of the calibration unit definitions for the corresponding calibration element of...

Page 276: ...ibration values for each entry in the calibration file Before writing any value to this file check the value against the low and high limit values to insure that it is within limits The write procedures in the receiving station do not check to see if a value is within limits The organization of this file also differs in that the complete file is broken up into four sub files Each sub file is organ...

Page 277: ...at may be selected for that particular element of configuration in File 25 9 3 15 FILE 23 CONTROL CFG LABELS This file contains the drive configuration labels One element is used to produce one label For example First element JOG REF Next element MASTER REF 9 3 16 FILE 24 CONTROL CAL UNITS This file contains the units associated with each of the labels defined for the control calibration values On...

Page 278: ...ing angle has been reached Additionally the motor field feedback is within the 10 setpoint and the drive is configured for the contactor to remain sealed upon RUN removal until ZERO SPEED 9 3 21 FILE 29 DDT LABELS This file contains all predefined label definitions for the digital data table One element is used to produce one label For example First element MAX_A_ALPHA spaces are shown as __ Next ...

Page 279: ...ement contains one high limit value 9 3 25 FILE 33 DRIVE CAL LO LIMS This file contains all of the predefined low limit values for each drive calibration value Each element contains one low limit value 9 3 26 FILE 34 DRIVE CAL DEFAULTS This file contains all of the predefined default values for drive calibration Each element contains one default drive calibration value For example First element 7 ...

Page 280: ...LE 38 DRIVE CAL This file contains all of the calibration values for each drive calibration entry At initial power up or a power up with default conditions request the default values in File 34 will be written into this file For example First element AD_REF Next element IARM_SPAN 9 3 31 FILE 39 SELECT LIST LABELS The select list table contains ASCII data that may be read but not written to Each el...

Page 281: ...part number and version number of the installed software 9 3 35 FILE 43 TIME ARRAY This file is organized as two long integer values of four bytes each The lower element value is a time reference that may be written with a time reference value by the master station If it is not written to it will default to a value of zero 0 The upper element value will be incremented six times for each line cycle...

Page 282: ... EXAMPLE ANALYZER CAL HI LIMS FILE 45 Analyzer 1 Analyzer 2 Element Element 0 9999 0 8 9999 0 1 9999 0 9 9999 0 2 2999 0 10 2999 0 3 9999 0 11 9999 0 4 9999 0 12 9999 0 5 0 0 13 0 0 6 0 0 14 0 0 7 0 0 15 0 0 Analyzer 3 Analyzer 4 Element Element 16 9999 0 24 9999 0 17 9999 0 25 9999 0 18 2999 0 26 2999 0 19 9999 0 27 9999 0 20 9999 0 28 9999 0 21 0 0 29 0 0 22 0 0 30 0 0 23 0 0 31 0 0 9 3 38 FILE ...

Page 283: ...ontrol for each channel This table must be used to generate configuration data changes Any data reference not contained in this table will be invalid and control action will be undefined The table is organized as a two dimension array with eight 8 by nineteen 19 unsigned short integer values for each of the four channels Each of the tables consists of a maximum of eight choices for each of the nin...

Page 284: ...om the data tables may not be read until the status indicates that the data sampling and storage is complete and ready for recovery The file number assignments are as follows File 52 The status of channel 1 Data file 56 File 53 The status of channel 2 Data file 57 File 54 The status of channel 3 Data file 58 File 55 The status of channel 4 Data file 59 Each of the four status files are organized a...

Page 285: ...type assigned while the lower 12 bits define the index into the table defined by the type For example if the type bits were 00 then the index value would be the offset into the Select List table The defined types and tables are as follows TYPE TABLE 0 Select List 1 Analog Data Table 2 Digital Data Table 3 Drive Calibration 4 Control Calibration 5 Drive Configuration 6 Control Configuration 7 Reser...

Page 286: ...Address Word 2 4 Digital Setpoint to ADDvantage32 4 1 Digital Setpoint to ADDvantage32 4 2 Digital Setpoint to ADDvantage32 4 3 Digital Setpoint to ADDvantage32 4 4 Digital Setpoint to ADDvantage32 4 5 Digital Setpoint to ADDvantage32 4 6 Digital Setpoint to ADDvantage32 4 7 Digital Setpoint to ADDvantage32 4 8 Digital Setpoint to ADDvantage32 4 9 Digital Setpoint to ADDvantage32 4 1 Digital Setpo...

Page 287: ... as a 32 bit integer with Word 1 being the least significant Word 2 as most significant This value can be up to 8 floating point values and will determine the overall size of the message As an example if only two analog values are intended to be sent as part of the AutoScan Write message the Number of Analog Setpoints parameter shall be set to two 2 and the total message length transferred to the ...

Page 288: ...ADDvantage 32 Advanced Control Module ACM 9 18 RSLogix 5 MSG configuration for AutoScan Write Figure 9 3 47 1 ...

Page 289: ...antage32 D016 thru D031 18 Digital Feedback from ADDvantage32 D032 thru D047 19 Digital Feedback from ADDvantage32 D048 thru D063 20 Digital Feedback from ADDvantage32 D064 thru D079 21 Digital Feedback from ADDvantage32 D080 thru D095 22 Digital Feedback from ADDvantage32 D096 thru D111 23 Digital Feedback from ADDvantage32 D112 thru D127 24 Digital Feedback from ADDvantage32 D128 thru D143 25 Di...

Page 290: ...ntage32 will return a packet 20 integers in length where the first 16 integers contain Analog Feedback data and the remaining four integers contain Digital Feedback data D000 through D063 RSLogix 5 MSG configuration for AutoScan Read Figure 9 3 47 2 62 VIRTUAL KEYBOARD 1 A R W DISPLAY 9 3 48 FILE 63 THROUGH 64 _MISC STATUS FILES 63 DOWNLOADING 2 I R W 64 RETURN FAULTS 2 I R W 9 3 49 FILE 65 THROUG...

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