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AD9888 Evaluation Board

 

EVAL-AD9888EB

 

 

Rev.

 

0  

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However, no responsibility is assumed by Analog Devices for its use, nor for any 
infringements of patents or other rights of third parties that may result from its use. 
Specifications subject to change without notice. No license is granted by implication 
or otherwise under any patent or patent rights of Analog Devices. Trademarks and 
registered trademarks are the property of their respective companies.

 

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Tel: 781.329.4700

 

www.analog.com

 

Fax: 781.326.8703

© 2003 Analog Devices, Inc. All rights reserved. 

GENERAL DESCRIPTION 

The EVAL-AD9888EB can be used both to demonstrate the 
performance of the AD9888 and to serve as an implementation 
example for design and layout. To aid in real-world evaluation, 
the EVAL-AD9888EB was designed to be connected as easily as 
possible into another PCB, such as a graphics controller board. 

REQUIREMENTS 

The EVAL-AD9888EB requires a 5 V power supply, graphics 
signals (through either of the 15-pin VGA connectors), and a 
means to program the internal chip registers. PC compatible 
hardware and software are provided for programming the 
internal chip registers. 

TYPICAL CONFIGURATION 

In most cases, this evaluation board will be used to digitize 
analog RGB graphics signals and pass the data on to another 
board. To do this, connect the graphics signals to either of the 
15-pin VGA connectors, supply 5 V to the board, and program 
the internal serial register. Supplying power and programming 
the chip are described later in this data sheet. The digitized data, 
generated clock signals, and control signals are passed off the 
board through the right-side Connector J3. 

POWER 

The EVAL-AD9888EB contains three 3.3 V voltage regulators, 
which supply power to the AD9888’s three power supplies (refer 
to the AD9888 Data Sheet). Best performance can be obtained 
from the AD9888 when the analog supply (V

D

) and the PLL 

supply (P

VD

) have their own regulators separate from the 

primary 3.3 V supply (V

DD

). The three regulators work 

nominally when supplied with 5 V, but will work with a range of 
voltages. Power is applied to the board through the right-side 
connector (Pins 1, 2, 41, and 42 of J3). Typically, power is 
supplied from another board, as is the case when using the 
UXGA panel driver board. 

SYNC SELECTION FOR J3 BOARD INTERFACE 

The EVAL-AD9883EB provides for raw Hsync and Vsync 
selection to connector J3 via the 3-pin jumpers labeled HS_SEL 
and VS_SEL. If the raw Hsync and Vsync are to be used by the 

 

Figure 1. The AD9888 Evaluation Board 

 

connected interface board (whether it be a panel driver board 
or other type of board), these jumpers should be placed 
appropriately depending on which video input is selected. If 
input 0 is selected, the jumpers should be placed in the 0 
position (as marked on the PCB); If 1 is selected, the jumpers 
should be placed in the 1 position. 

CHIP REGISTER NAMING CONVENTION 

There are several references in this data sheet to specific control 
registers in the AD9888. The convention used in this data sheet 
is to specify the register number in hex, followed by an “h” and 
by the bit number within the register. For example, [12h7] 
means Register 12, Bit 7. 

PROGRAMMING THE INTERNAL CHIP REGISTERS 

Hardware and software are provided for programming the 
AD9888 internal registers. The hardware consists of a standard 
printer cable and a receiver chip located on the panel driver 
board. The programming signals come onto the EVAL-
AD9888EB through Pins 38 and 39 on Connector J3. The 
software is included on the installation CD-ROM and is 
described in the Setup Software section. 

 

 

Summary of Contents for EVAL-AD9888EB

Page 1: ... the right side Connector J3 POWER The EVAL AD9888EB contains three 3 3 V voltage regulators which supply power to the AD9888 s three power supplies refer to the AD9888 Data Sheet Best performance can be obtained from the AD9888 when the analog supply VD and the PLL supply PVD have their own regulators separate from the primary 3 3 V supply VDD The three regulators work nominally when supplied wit...

Page 2: ...L AD988x device It also includes the display interface board configuration software and a PLL divisor calculator PLL Settings The PLL settings are contained in Registers 01h to 04h The PLL Divisor setting 12 bits can be set bit by bit the value toggles when clicking on the bit by setting a value in decimal for Registers 01h and 02h by setting the 12 bit value in decimal or by moving the control ba...

Page 3: ... Sheet for a functional description of these bits SOG and Clamp Control Register 10h contains bits for controlling the SOG threshold and Clamp selection functions Register 11h contains bits for adjusting the Sync separator threshold The 5 bit Reg 10h7 3 SOG Threshold can be modified bit by bit by changing the 5 bit decimal value or by sliding the control bar The user can toggle each Clamp selectio...

Page 4: ...00 P 1688 135 000 10 100 1280 1024 85 Hz 91 100 P 1730 157 500 11 100 UXGA 1280 1024 60 Hz 75 000 P 2160 162 000 11 100 1280 1024 65 Hz 81 300 P 2160 175 500 11 100 1280 1024 70 Hz 87 500 P 2160 189 000 11 101 1280 1024 75 Hz 93 800 P 2160 202 500 11 101 1 PLL divisor to the chip should be an odd integer Chip divide ratio Input N offset of 1 2 The VCO range and charge pump current settings are pre...

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