Altera MAX V CPLD Reference Manual Download

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101 Innovation Drive
San Jose, CA 95134

www.altera.com

MNL-01061-1.1

Reference Manual

MAX V CPLD Development Board

MAX V CPLD Development Board Reference Manual

Summary of Contents for MAX V CPLD

Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com MNL 01061 1 1 Reference Manual MAX V CPLD Development Board Subscribe MAX V CPLD Development Board Reference Manual ...

Page 2: ...on legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly ag...

Page 3: ...ments 2 5 Configuration 2 5 CPLD Configuration over Embedded USB Blaster 2 5 CPLD Configuration using External USB Blaster 2 6 Status Elements 2 6 Setup Elements 2 7 Clock Circuitry 2 7 Connectors 2 8 GPIO Headers 2 8 PC Speaker Header 2 10 DC Motor Headers 2 11 General User Input Output 2 13 User Defined Push Button Switches 2 13 User Defined LEDs 2 13 Off Chip EEPROM 2 14 I2 C EEPROM 2 14 SPI EE...

Page 4: ...iv Contents MAX V CPLD Development Board Reference Manual September 2015 Altera Corporation ...

Page 5: ... interface to external functions or devices f For more information on the MAX V CPLD device family refer to the MAX V Device Handbook Board Component Blocks The board features the following major component blocks MAX V CPLD 5M570ZF256C5N in a 256 pin FineLine BGA FBGA package 570 logic elements LEs 440 equivalent macrocells 8 192 bits user flash memory UFM 4 global clocks 159 user I Os 1 8 V core ...

Page 6: ...of the MAX V CPLD development board Handling the Board When handling the board it is important to observe the following static discharge precaution c Without proper anti static handling the board can be damaged Therefore use anti static handling precautions when touching the board Figure 1 1 MAX V CPLD Development Board Block Diagram DC Motor Header 1 EPM240M100 Embedded USB Blaster USB 2 0 x1 x9 ...

Page 7: ... GERBER files for the development board reside in the MAX V CPLD development kit documents directory f For information about powering up the board and installing the demonstration software refer to the MAX V CPLD Development Kit User Guide This chapter consists of the following sections Board Overview Featured Device MAX V CPLD on page 2 3 Configuration Status and Setup Elements on page 2 5 Clock ...

Page 8: ... J7 USB Type B Connector J4 Motor Control Header 1 J5 Power LED D1 User Push Button Switches S1 S2 MAX II CPLD EPM240M100C4N For embedded USB Blaster U4 Motor Control Header 2 J10 Speaker Header J9 Footprint for I2C EEPROM U6 Footprint for SPI EEPROM U8 Power Regulator U7 USB LED D3 Capacitor Sense Button CPB1 VAR_VCCIO Voltage Output Selection Jumper U7 Table 2 1 MAX V CPLD Development Board Comp...

Page 9: ...le ended input clock for the MAX V CPLD X1 6 MHz oscillator 6 MHz input clock for the FTDI USB 2 0 PHY device Y1 24 MHz oscillator 24 MHz input clock for the MAX II CPLD EPM240M100 Connectors J6 J7 GPIO headers Two general purpose 2x40 pin 0 1 inch expansion headers J9 PC speaker header A 4 pin PC speaker header which connects to the MAX V CPLD I O bank 2 J5 J10 DC motor headers Two motor headers ...

Page 10: ...Table 2 3 MAX V CPLD Device Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U5 MAX V CPLD 256 pin FBGA package 570 LEs lead free Altera Corporation 5M570ZF256C5N www altera com Figure 2 2 5M570ZF256C5N Device I O Bank Diagram Note 1 Note to Figure 2 2 1 This figure is a top view of the silicon die and is a gr...

Page 11: ... this optional method to configure the CPLD you have to mount the JTAG connector or header to the back of the board CPLD Configuration over Embedded USB Blaster The USB Blaster is implemented using a USB Type B connector J4 a FTDI USB 2 0 PHY device U3 and an Altera MAX II CPLD EPM240M100 U4 This allows the configuration of the MAX V CPLD using a USB cable which connects between the USB port on th...

Page 12: ... II Programmer running on a PC The external USB Blaster connects to the board through the JTAG connector Figure 2 3 illustrates the JTAG chain Status Elements This section describes the status elements The development board includes two status LEDs which connects to the MAX V CPLD Table 2 5 lists the LED board references names and functional descriptions Figure 2 3 JTAG Chain MAX V CPLD 5M570ZF256...

Page 13: ... MHz crystal oscillator which provides the input clock for the USB 2 0 PHY device Table 2 16 lists the oscillator component reference and the manufacturing information Table 2 6 Board Specific LEDs Component References and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website D1 Blue LED Lite On LTST C170TBKT www liteon com D3 Green LEDs L...

Page 14: ... GPIO connector A pin AGPIO_4 N3 J6 5 GPIO connector A pin AGPIO_5 N2 J6 6 GPIO connector A pin AGPIO_6 N1 J6 7 GPIO connector A pin AGPIO_7 M3 J6 8 GPIO connector A pin AGPIO_8 M2 J6 9 GPIO connector A pin AGPIO_9 M1 J6 10 GPIO connector A pin AGPIO_10 L3 J6 11 Power 5VIN_CONN 5 V J6 12 Ground GND J6 13 GPIO connector A pin AGPIO_11 3 3 V L1 J6 14 GPIO connector A pin AGPIO_12 L2 J6 15 GPIO conne...

Page 15: ...s and Functions Part 1 of 2 Board Reference Description Schematic Signal Name I O Standard MAX V CPLD Device Pin Number J7 1 GPIO connector B pin BGPIO_P_1_R Variable VCCIO voltage 1 2 V to 3 3 V D15 J7 2 GPIO connector B pin BGPIO_P_2_R D16 J7 3 GPIO connector B pin BGPIO_N_1_R C14 J7 4 GPIO connector B pin BGPIO_N_2_R C15 J7 5 GPIO connector B pin BGPIO_P_3_R E15 J7 6 GPIO connector B pin BGPIO_...

Page 16: ...3 3VIN_CONN 3 3 V J7 30 Ground GND J7 31 GPIO connector B pin BGPIO_27 Variable VCCIO voltage 1 2 V to 3 3 V L16 J7 32 GPIO connector B pin BGPIO_28 L15 J7 33 GPIO connector B pin BGPIO_29 L14 J7 34 GPIO connector B pin BGPIO_30 M16 J7 35 GPIO connector B pin BGPIO_31 M15 J7 36 GPIO connector B pin BGPIO_32 M14 J7 37 GPIO connector B pin BGPIO_33 L13 J7 38 GPIO connector B pin BGPIO_34 M13 J7 39 G...

Page 17: ... O Standard MAX V CPLD Device Pin Number J9 1 Speaker header I O pin MAX_SPK_0 Variable VCCIO voltage 1 2 V to 3 3 V N15 Speaker header I O pin MAX_SPK_1 N16 Speaker header I O pin MAX_SPK_2 P15 Speaker header I O pin MAX_SPK_3 P14 Speaker header I O pin MAX_SPK_4 H12 Speaker header I O pin MAX_SPK_5 J12 Speaker header I O pin MAX_SPK_6 A8 Speaker header I O pin MAX_SPK_7 A7 J9 4 Power VAR_VCCIO J...

Page 18: ...RL C5 J5 1 Power VAR_VCCIO J5 5 Ground GND J10 3 Motor header 2 I O pin MAX_MOTOR_2_0 A10 Motor header 2 I O pin MAX_MOTOR_2_1 A15 Motor header 2 I O pin MAX_MOTOR_2_2 A11 Motor header 2 I O pin MAX_MOTOR_2_3 A13 Motor header 2 I O pin MAX_MOTOR_2_4 A12 Motor header 2 I O pin MAX_MOTOR_2_5 B16 J10 2 Motor header 2 feedback signal A MOTOR_2_FB_A D12 J10 4 Motor header 2 feedback signal B MOTOR_2_FB...

Page 19: ...be driven to the LEDs from the CPLD designs loaded into the MAX V CPLD device There is no board specific function for these LEDs Table 2 17 lists the user defined LED schematic signal names and their corresponding MAX V CPLD pin numbers Table 2 15 User Defined Push Button Switch Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard MAX V CPLD Device Pi...

Page 20: ...lists the I2C EEPROM device pin assignments signal names and functions The signal names and types are relative to the MAX V CPLD device in terms of I O setting and direction Table 2 18 User Defined LED Component Reference and Manufacturing Information Board Reference Device Description Manufacturer Manufacturer Part Number Manufacturer Website D7 D8 Green LEDs Lumex Inc SML LX1206GC TR www lumex c...

Page 21: ...ry 1 Microchip 24LC08BT I OT www microchip com Note to Table 2 20 1 This component is a compatible unit which can be used on the development board The MAX V CPLD development kit does not include this component Table 2 21 SPI EEPROM Pin Assignments Schematic Signal Names and Functions Board Reference Description Schematic Signal Name I O Standard MAX V CPLD Device Pin Number U8 1 SPI chip select si...

Page 22: ...VCCINT CPLD core voltage 2 VAR_VCCIO 1 2 3 3 VCCIO CPLD I O bank 2 variable voltage 3 3 3V 3 3 VCCIO Power for I O bank 1 and EEPROM 4 5V 5 0 5V_USB Power up USB peripheral Table 2 24 Power Supply Rail Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U7 400 mA 2 25 MHz synchronous step down DC DC converter Lin...

Page 23: ...Version Changes September 2015 1 1 Corrects descriptions of J7 2 J7 3 J7 6 and J7 7 in GPIO Header B Schematic Signal Names and Functions on page 2 9 January 2011 1 0 Initial release Contact 1 Contact Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Product literature Website www altera com literature Non t...

Page 24: ...hic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of...

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