eZ8 CPU
User Manual
UM012811-0904
Address
Space
13
Address Space
INTRODUCTION
The eZ8 CPU can access three distinct address spaces:
•
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and I/O port control registers.
•
The Program Memory contains addresses for all memory locations having executable
code and/or data.
•
The Data Memory contains addresses for all memory locations that hold data only.
REGISTER FILE
The eZ8 CPU supports a maximum of 4096 consecutive bytes (registers) in the Register
File. The Register File is composed of two sections - control registers and general-purpose
registers. The upper 256 bytes are reserved for control of the eZ8 CPU, the on-chip periph-
erals, and the I/O ports. These 256 registers are always located at addresses from
F00H
to
FFFH
.
When instructions execute, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
Some eZ8 CPU products contain a Register File that is less than the maximum of 4096
bytes. For eZ8 CPU products with less than 4096B in the Register File, reading from an
unavailable Register File addresses returns an undefined value. Writing to an unavailable
Register File addresses produces no effect. Refer to the device-specific Product Specifica-
tion to determine the number of registers available in the Register File as well as descrip-
tions of the peripheral and I/O control registers.
CPU Control Registers
Within the 256 registers reserved for control, there are four eZ8 CPU control registers that
are always at the same register addresses. These four eZ8 CPU control registers (see
Table 6) are the Stack Pointer High Byte, Stack Pointer Low Byte, Register Pointer and
Flags registers. For more information on the operation of the eZ8 CPU control registers,
please refer to the Architectural Overview chapter.
