UM012811-0904
Architectural
Overview
eZ8 CPU
User Manual
3
Instruction Cycle Time
The instruction cycle times vary from instruction to instruction, allowing higher perfor-
mance given a specific clock speed. Minimum instruction execution time for standard
CPU instructions is two clock cycles (only the BRK instruction executes in a single cycle).
Because of the variation in the number of bytes required for different instructions, delay
cycles can occur between instructions. Delay cycles are added any time the number of
bytes in the next instruction exceeds the number of clock cycles the current instruction
takes to execute. For example, if the eZ8 CPU executes a 2-cycle instruction while fetch-
ing a 3-byte instruction, a delay cycle occurs because the Fetch Unit has only two cycles to
fetch the three bytes. The Execution Unit is idle during a delay cycle.
PROGRAM COUNTER
The Program Counter contains a 16-bit counter and a 16-bit adder. The Program Counter
monitors the address of the current memory address and calculates the next memory
address. The Program Counter increments automatically according to the number of bytes
fetched by the Fetch Unit. The 16-bit adder increments and handles Program Counter
jumps for relative addressing.
eZ8 CPU CONTROL REGISTERS
The eZ8 CPU contains four CPU control registers that are mapped into the Register File
address space. These four eZ8 CPU control registers are:
•
Stack Pointer High Byte
•
Stack Pointer Low Byte
•
Register Pointer
•
Flags
The eZ8 CPU register bus can access up to 4K (4096) bytes of register space. In all eZ8
CPU products, the upper 256 bytes are reserved for control of the eZ8 CPU, the on-chip
peripherals, and the I/O ports. The eZ8 CPU control registers are always located at
addresses from
FFCH
to
FFFH
