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The Zeroplus Logic Analyzer

Installation Guide

The Zeroplus Logic Analyzer Installation Guide

Page 1

Index

Preface ............................................................................................................. 2

1 Features of the Zeroplus Logic Analyzer ................................................ 3

1.1 Package Contents ............................................................................................ 3
1.2 Introduction ...................................................................................................... 5
1.3 Hardware Specifications................................................................................... 8
1.4 System Requirements ...................................................................................... 9

1.4.1 Operating System Requirements .......................................................... 9
1.4.2 Hardware System Requirements........................................................... 9

1.5 Device Maintenance and Safety..................................................................... 10

2 Installation ................................................................................................ 12

2.1 Software Installation ....................................................................................... 12
2.2 Hardware Installation ..................................................................................... 14
2.3 Tips and Advice .............................................................................................. 16
2.4 Flow of software operation ............................................................................. 18

3 Introduction to Logic Analysis ............................................................... 19

3.1 Logic Analysis ................................................................................................ 19

Task 1. Clock Source (Frequency) and RAM Size set up.................... 19
Task 2. Trigger Properties Setup ......................................................... 21
Task 3. Signal/Bus Trigger Edge Setup ............................................... 26
Task 4. Run to Acquire Data ................................................................ 26

3.2 Bus Logic Analysis ......................................................................................... 28

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Summary of Contents for LAP-321000U-A

Page 1: ......

Page 2: ...ng System Requirements 9 1 4 2 Hardware System Requirements 9 1 5 Device Maintenance and Safety 10 2 Installation 12 2 1 Software Installation 12 2 2 Hardware Installation 14 2 3 Tips and Advice 16 2 4 Flow of software operation 18 3 Introduction to Logic Analysis 19 3 1 Logic Analysis 19 Task 1 Clock Source Frequency and RAM Size set up 19 Task 2 Trigger Properties Setup 21 Task 3 Signal Bus Trig...

Page 3: ...tive electrical current sensing device Users must carefully read instructions and procedures pertaining to installation and operation Any instrument connected to the unit should be properly grounded A pair of anti static gloves is strongly recommended when performing a task with the device To ensure accuracy and consistency of output data use of the bundled components is strongly recommended User ...

Page 4: ...he Zeroplus Logic Analyzer 1 1 Package Contents Verify the package contents before discarding packing materials The following components should be included with your product For assistance please contact our nearest distributor Table 1 1 Parts list for retail packages Models LAP 16128U LAP 32128U A LAP 321000U A LAP 322000U A Logic Analyzer 1 1 1 1 16 Pin Testing Cable 0 1 1 1 Pin Testing Cable 2 ...

Page 5: ...r Installation Guide Page 4 Fig 1 1 Logic Analyzer 16 Pin x 1 8 Pin x 2 Fig 1 2 Testing Cables Fig 1 3 Probes varied depending on models Fig 1 4 USB Cable Fig 1 5 Getting Started Guide Fig 1 6 Driver CD Fig 1 7 1 Pin External Clock Wire White Fig 1 8 2 Pin Ground Wire Black ...

Page 6: ...LAP 16128U LAP 32128U A LAP 321000U A and LAP 322000U A all share the same external features as illustrated in the following figures Fig 1 9 A view of the Zeroplus Logic Analyzer LAP A Series see Fig 1 12 for detailed information on the Signal Connectors Fig 1 10 Side view of the Zeroplus Logic Analyzer which draws its power from the USB connection ...

Page 7: ...y be adjusted Gently pull the plate away from the analyzer rotate it 90 and release it Fig 1 12 Rear view of the Zeroplus Logic Analyzer LAP A Series Port A A0 A7 Port B B0 B7 Port C C0 C7 Port D D0 D7 For the External Clock connection For grounding test circuits For extended modules or devices not designated to be analyzed For signal transmission to active other instruments ...

Page 8: ...r grounding the Logic Analyzer with a given external module to be analyzed Table 1 3 Definitions and Functions of pins for advanced models 1 R_O Read Out When the Logic Analyzer is about to upload data from memory to the PC the R_O will send a Rising Edge signal of DC3 3V When the upload is finished a Falling Edge signal is sent T_O Trigger Out When a trigger condition is established the T_O will ...

Page 9: ...1 5 Hardware specifications of LAP A Model Items Type LAP 16128 LAP 32128U A LAP 321000U A LAP 322000U Interface USB 2 0 1 1 Operating System 98SE ME 2000 XP Power Supply USB 1 1 USB 2 0 Recommended Channels 16 32 Bandwidth 75MHz Memory 4M Bits Memory Depth Per Channel 128 Kbits 128 KBits 1 MBits 2 MBits Internal Clock Rate asynchronous 100 200 MHz Max External Clock synchronous Max 100MHz Trigger...

Page 10: ...ws 98 98 Second Edition supported 2 Windows ME supported 3 Windows 2000 Professional Server Family supported 4 Windows XP Home Professional Editions 32 Bit versions supported 1 4 2 Hardware System Requirements z CPU Windows NT 98 98 SE 166 MHz or above Windows 2000 XP 300 MHz or above strongly suggest 900 MHz or above We have tested various 32 Bit and 64 Bit CPUs Overall we find that all 32 Bit CP...

Page 11: ...ld affect its operation Cleaning x Use a soft damp cloth with a mild detergent to clean x Do not immerse or spray any liquid on the Zeroplus Logic Analyzer x Do not use harsh chemicals or cleaners containing substances such as benzene toluene xylene or acetone Table 1 8 Electrical Specifications Items Minimum Typical Maximum Working Voltage DC 4 5 V DC 5 0 V DC 5 5 V Current at Rest 200 mA Current...

Page 12: ...egree 1 No pollution or only dry non conductive pollution occurs This pollution has no effect Pollution Degree 2 Normally only non conductive pollution occurs Occasionally however temporary conductivity caused by condensation must be expected Pollution Degree 3 Conductive pollution occurs or dry non conductive pollution occurs which becomes conductive due to condensation In such conditions equipme...

Page 13: ...n Chapter 1 would follow identical procedures Step 1 Insert the driver CD ROM in the PC CD drive Step 2 Execute the installation program Go to the START menu click START click Run click Browse select Setup exe file in the appropriate model folder and then click OK It is recommended that all other programs are closed while installation proceeds Step 3 Choose the desired language Step 4 Click Next t...

Page 14: ...The Zeroplus Logic Analyzer Installation Guide The Zeroplus Logic Analyzer Installation Guide Page 13 ...

Page 15: ... 1 Plug the fixed end of the cables into the LA Fig 2 1 2 Plug the loose ends into the connectors on the circuit board to be analyzed Fig 2 2 Note The following sequence must be observed when connecting the connectors into the circuit board A0 Brown A1 Red A2 Orange and so on 3 The circuit board must be grounded to the Logic Analyzer with the connecting cables Fig 2 3 Step 1 Plug the thin male end...

Page 16: ...ic Analyzer Fig 2 4 5 Plug the thin end into the computer Fig 2 5 At this point the computer should be able to detect the Logic Analyzer and finalize the installation for hardware connection For further information refer to the Troubleshooting and Frequently Asked Questions FAQ chapters in the User Manual Fig 2 6 An assembly of Laptop Logic Analyzer and a testing board ...

Page 17: ...d frequency 2 If the signal connector does not work well with the pins on the test board try using the supplied probes Fig 2 7 Probes supplied with the Zeroplus Fig 2 8 Fig 2 9 3 Usages of probes 3 1 Take the loose end of the cable and insert it into the clip 3 2 Compress the probe as shown to reveal 2 metal prongs Fig 2 8 3 3 Place the metal prongs on a metal connector on the motherboard and rele...

Page 18: ...hen measuring for a long period Compression makes memory more efficient 7 Trigger condition depends on the test board If triggering does not work well try narrowing the trigger conditions and optimize them repeatedly 8 If a test board has a lower frequency than Logic Analyzer sample signals according to the external clock 9 When clocking by an external clock filter extra signals with the Enable fu...

Page 19: ...The Zeroplus Logic Analyzer Installation Guide The Zeroplus Logic Analyzer Installation Guide Page 18 2 4 Flow of software operation ...

Page 20: ... analytical operations are the Logic Analysis and the Bus Analysis which are fundamental to all further applications 3 1 Logic Analysis Logic Analysis is meant for a single signal analysis Section 3 1 gives detailed instructions on the software s basic setup Basic Software setup of the Logic Analysis Task 1 Clock Source Frequency and RAM Size set up Step 1 Click icon or Click Sampling Setup from B...

Page 21: ... Tool Bar as Fig 3 2 shows Tip Connect the signal output pin of the tested board to the Signal connector of Logic Analyzer to measure it using the internal clock of Logic Analyzer Fig 3 2 Clock source drop down menu External Clock Synchronous Clock Click on External Clock and then select Rising Edge or Falling Edge as the trigger condition of the DUT In the Frequency column type the frequency of t...

Page 22: ...vs Compression and channels Model No RAM sizes channel Channels available Compression Mode Enable Mode RAM size channel Channels available Compression Mode Enable Mode LAP 16128U 2K 128K 16 channels Available 256K 16 channels Disable LAP 32128U A 2K 128K 32 channels Available 256K 16 channels Disable LAP 321000U A 2K 1M 32 channels Available 2M 16 channels Disable LAP 322000U A 2K 2M 32 channels A...

Page 23: ...l TTL CMOS 5V CMOS 3 3V and ECL Users also may define their own voltage from 6V to 6V to fit with their DUT Port A represents the pins from A0 A7 on the signal connector of the Logic Analyzer and so do Ports B C and D The voltage of each port may be configured independently Fig 3 5 Trigger Properties Error Step 3 Trigger Count Type the numbers or select the number from the pull down menu of the Co...

Page 24: ...ay Time and Clock can t be applied at the same time 1 Trigger Page Click Trigger Page then Type the numbers or select the numbers from the pull down menu of the Page on the Tool Bar or Click the pull down menu of the Trigger Page on the Trigger Delay page of the Trigger Properties dialogue as shown in Figs 3 9 3 10 and 3 11 The page numbers selected will be displayed on the screen Tip The Trigger ...

Page 25: ...ck the Delay Time and Clock then type the numbers into the column of the Trigger Delay Time or type numbers into the Trigger Delay Clock at the Trigger Delay page of the Trigger Properties dialogue as 0 and Fig 0 Or type the numbers into the column of Trigger Delay on the Tool Bar The system will display the wave start Tip The formula of Delay Time and Clock is Trigger Delay Time Trigger Delay Clo...

Page 26: ...gger Position on the Trigger Delay page of the Trigger Properties dialogue as shown in Figs 3 12 3 13 3 14 and 3 15 The Trigger Position percentages selected will be displayed where counted from the right side of the screen of the system Fig 3 12 Trigger Position Drop down menu Fig 3 13 Trigger Position 0 Fig 3 14 Trigger Position 10 Fig 3 15 Trigger Position 70 Step 6 Click OK to confirm the setu...

Page 27: ...18 Fig 3 16 Trigger Left click Fig 3 17 Trigger Right Click Fig 3 18 Trigger menu Task 4 Run to Acquire Data 1 Single Run Click the Single Run icon from the tool bar or press START button on top of Logic Analyzer or press F5 then activate the signal from the DUT to the Logic Analyzer to acquire the data shown in the wave display area 2 Repetitive Run Click the Repetitive Run icon from the tool bar...

Page 28: ...Page 27 Fig 3 19 Click icon to view all the data 3 Stop to End Run Click the Stop icon to End the Run Tip If the status stays displays Waiting with no signal output as shown in Fig 3 20 click the stop icon to end the run check the setup again and try the run process again Fig 3 20 Waiting Status ...

Page 29: ... 1 Step 2 Group Signals into a Bus Click Channels setup on Bus Signal of menu bar or click icon The dialogue window shown in Fig 3 21 will appear Fig 3 21 Channel setup Rename the bus and set up the signals of the bus as shown in Fig 3 22 Fig 3 22 Renaming Bus 1 Click the column with blue then type the given name of the bus and then press enter to confirm it 2 Go to the relative channels show as s...

Page 30: ...nnels on area 6 of Fig 3 23 then click Delete Bus Signal to delete it 2 Delete All click Delete All to delete all bus signals on area 6 of Fig 3 23 3 Restore Defaults click Restore Defaults to restore the dialogue of Channels Setup as shown in Fig 3 21 Step 3 Set Trigger condition 1 Highlight the bus which will be triggered then click icon or select Bus from the Trigger of the Menu bar the dialogu...

Page 31: ...o set the trigger condition of the bus 4 Click OK Step 4 Click run and activate the signal from the tested board to the system to get the result as shown in Fig 3 26 Tip Click icon to view all data and then select the wave analysis tools to analyze the waves Set Value is 5E as Hexadecimal and set Operator equal to then click OK Click run and activate the signal from the tested board to the system ...

Page 32: ...ei County 235 Taiwan R O C Tel 886 2 6620 2225 212 Effie 223 Anthony Fax 886 2 2223 4362 Best Measure Best Quality www zeroplus com tw 6F No 265 Wuling Rd North District Hsinchu City 300 Taiwan R O C Tel 886 3 542 6637 87 Fax 886 3 542 491 Instrument Sales Department ...

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