14
CONFIDENTIAL
DOC-USR-0239-04
____________________________________________________________________________________
Z3 Technology, LLC
♦
100 N. 8th St. STE 250
♦
Lincoln, NE 68508-1369 USA
♦
+1.402.323.0702
8.0
THERMAL MANAGEMENT
The Z3-Q603-RPS system is comprised of a CPU module board, one Application board which contains the
hardware implementation of the input and output circuits and one Connector board which contains the
major I/O jacks such as Ethernet and power jacks.
The system requires that heat is removed from the CPU chip on the module board and from the FPGA chip
on the Application board and dissipated into the environment in order to maintain its operating temperature
specification. It may be necessary to also remove heat from other components on the module or application
boards depending on the environmental requirements of the final application. Keeping the CPU and FPGA
chips within their allowed operating temperatures is critical for the operation of the encoder system.
The system designer is responsible for implementing the cooling mechanisms necessary for any given
application.
The Z3-Q603-RPS board set as provided from Z3 Technology includes a block of aluminum which is thermally
coupled to the CPU chip. This aluminum block is meant to be attached to a heat sink such as a metal
enclosure or other material capable of removing heat from the system.
Note that the aluminum block is a good thermal conductor but is a poor thermal sink. The aluminum block is
not efficient at radiating the heat from the CPU to air, it must be thermally connected to a device that can
dissipate the thermal energy.
The FPGA chip must also be managed carefully. This chip is located in the Application board, which is the
PCB “in the middle” of the stack, making its ther
mal management particularly important and a little bit
challenging. The system designer must assure some method to remove heat from the FPGA device. At a
minimum the system designer must ensure good cool air circulation in some pattern that heat is not trapped
between the Application board and the other two boards.
The thermal solution implemented by the user will determine the operating temperature range of the
system. The thermal solution must maintain the junction temperature of the CPU and FPGA chips within the
limits specified by the component’s datasheet. The CPU chip datasheet specifies a junction temperature Tj
max of 105°C, and 3GPP-mode ambient operating temperature of -20° to +60°C, while the FPGA datasheet
specifies a max junction temperature of +105
°C.
Both CPU and FPGA chips have temperature sensors as part of their design, so it is possible to measure the
junction temperature of these devices directly. These temperatures are provided on the encoder’s web GUI in
the “Status” tab, in the “Temperature Status” section.
Proper operation of the module requires that the thermal solution employed is capable of maintaining the
operation temperature of the CPU between -5°C and +100°C, and the temperature of the FPGA between -
10°C and +105°C. Ideally both CPU and FPGA max temperature should be maintained below +95°C.
