19
HE4K-DCK-1x & FV4K-DCK-1x
HARDWARE SPECIFICATION
CONFIDENTIAL
DOC-USR-0100-09
____________________________________________________________________________________
Z3 Technology, LLC
♦
100 N. 8th St. STE 250
♦
Lincoln, NE 68508-1369 USA
♦
+1.402.323.0702
7.1.5
J5
–
Optional Auxiliary Power
It is possible to provide power to the FCB-ER8300 camera from an external source, using J5. In that
case, 0 Ohm resistor R9 must be removed to disconnect the internal power supply from J5 and J1.
When using internal power (from the I/O Jack PCB) R9 must be populated with a 0 Ohm resistor and
J5 must be left unconnected. J5 is normally not populated on the IFE board.
The pin assignment of J5 is shown in the table below.
When populated, the connector used is a Hisrose DF13-4P-1.25DSA.
Pin
Signal
1
Ground
2
+12V
3
+12V
4
Ground
Table 7 IFE PCB J5 Pin Out
7.1.6
J6
–
Optional FPGA Debug and Expansion
Connector J6 exposes I/O pins from the FPGA. It can be used for FPGA debugging or to connect
additional devices to the FPGA.
J6 is not populated on the PCB.
The pin assignment of J6 is as shown in the table below.
Pin Signal
Pin Signal
1
No connection
2
+3.3V
3
DEB_CK, FPGA pin K4
4
DEB_D16, FPGA pin E2
5
DEB_D15, FPGA pin F3
6
DEB_D14, FPGA pin F1
7
DEB_D13, FPGA pin G2
8
DEB_D12, FPGA pin G1
9
DEB_D11, FPGA pin H3
10 DEB_D10, FPGA pin J4
11 DEB_D9, FPGA pin H1
12 DEB_D8, FPGA pin K5
13 DEB_D7, FPGA pin J1
14 DEB_D6, FPGA pin J2
15 DEB_D5, FPGA pin K1
16 DEB_D4, FPGA pin J3
17 DEB_D3, FPGA pin L1
18 DEB_D2, FPGA pin K3
19 DEB_D1, FPGA pin L2
20 GND
Table 8 IFE PCB J6 Pin Out
7.2
FV4K Interface Front End PCB
The FV4K Interface Front End PCB contains input circuits supporting a ER8300 camera or micro-HDMI
video input at up to 4K at 30 fps, a analog composite video input and a multi-format digital input
