CLM920 TD3 LTE Module Hardware Usage Guide
Shanghai Yuge Information Technology co., LTD
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I2S_CLK
IO I2S clock
VOH
1.35
1.8
2
VOL
0
0.45
VIH
1.2
1.8
2
VIL
-0.3
0.6
The following figure shows the reference design of the CLM920 TD3 connected to the
NAU8810:
Figure 3-24 I2S to analog voice map
3.15 MCLK interface
The CLM920 TD3 module provides one MCLK and provides a 12.288M clock output.
This interface is mainly used to connect the MCLK of the CODEC chip. The main clock
frequency of the NAU8810 is supported by default.
Table 3-24 MCLK Pin Definitions
Pin
Signal
name
I/O Description
Param
eter
Level value (V)
Remarks
Min
Typical Max
116 MCLK D0
I2S master
clock
VOH
1.35
1.8
2
The default output
is 12.288M
VOL
0
0.45
