YUGE CLM920 TD3 Page 49 Usage Manual Download

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CLM920 TD3 LTE Module Hardware Usage Guide

Shanghai Yuge Information Technology co., LTD

- 49 -

VOH 0.75*

VDD_Px

2.95

VDD_Px 2.95V voltage

domain

VOL 0

0.125*
VDD_Px

2.95V voltage
domain

SDC2_
CMD

SDIO bus
command

VOH 1.35

1.8

1.8V voltage
domain

VOL 0

0.45

1.8V voltage
domain

VIH

1.27

1.8

1.8V voltage
domain

VIL

-0.3

0.6

1.8V voltage
domain

VOH 0.75*

VDD_Px

2.95

VDD_Px 2.95V voltage

domain

VOL 0

0.125*
VDD_Px

2.95V voltage
domain

VIH

0.625*
VDD_Px

2.95

VDD_Px
+ 0.3

2.95V voltage
domain

VIL

-0.3

0.25*
VDD_Px

2.95V voltage
domain

VDD_
SDIO

SDIO bus
pull-up
power
supply

IO maximum output 50MA, output
1.8V/2.85V configurable

Cannot be
used for SD
card power
supply

The SD card reference design of the CLM920 TD3 module is shown in the figure below

：

Summary of Contents for CLM920 TD3

Page 1: ...e CLM920 TD3 LTE Module Hardware Usage Guide Number of Pages 79 Produce Version V1 0 Date 2019 5 6 CLM920 TD3 LTE Module Hardware Usage Guide V1 0 Shanghai Yuge Information Technology co LTD All right...

Page 2: ...CLM920 TD3 LTE Module Hardware Usage Guide Shanghai Yuge Information Technology co LTD 2 Update records Version Date Author Description V1 0 20190506 David Initial...

Page 3: ...esign 28 3 3 2 Power reference circuit 29 3 3 3 VDD_SDIO 1 8V 2 85V Voltage output 31 3 3 4 VDD_EXT 1V8 Voltage output 31 3 4 Switching machine reset mode 31 3 4 1 Boot 31 3 4 2 Boot timing 32 3 4 3 P...

Page 4: ...apter overview 63 4 2 GNSS reception performance 63 4 3 Working frequency 64 4 4 Conducted radio frequency measurement 65 4 4 1 Test environment 65 4 4 2 Test Standard 65 4 5 Conducted receiving sensi...

Page 5: ...gure 3 5 DC switching power supply reference circuit 30 Figure 3 6 PMOS tube control power switch reference circuit 30 Figure 3 7 Startup timing diagram 32 Figure 3 8 Power on reference circuit 33 Fig...

Page 6: ...ostrip line 60 Figure 3 33 The complete structure of the multilayer PCB strip line 60 Figure 3 34 Reference ground is the third layer PCB microstrip transmission line structure 61 Figure 3 35 RF conne...

Page 7: ...n definition 51 Table 3 24 MCLK Pin Definitions 52 Table 3 25 WLAN pin definitions 53 Table 3 26 SGMII interface pin definition 55 Table 3 27 ADC Pin Definitions 56 Table 3 28 Antenna interface pin de...

Page 8: ...Table 5 3 Working voltage of CLM920 TD3 module 72 Table 5 4 CLM920 TD3 ESD Features 73 Table 5 5 CLM920 TD3 reliability test 73 Table 7 1 Reflow process parameter table 79 Table 8 1 Abbreviations 80 T...

Page 9: ...less solution product CLM920 TD3 module It is intended to describe the hardware components and functional characteristics of the module solution application interface definition and usage instructions...

Page 10: ...0Mbps 150Mbps and fully supports VOLTE and SRLTE and supports embedded operating systems such as Windows7 Windows8 Windows10 Android Linux The CLM920 TD3 module can be used in the following applicatio...

Page 11: ...iDou Compass The module does not support diversity GPS and voice functions by default The GNSS function is optional The diversity function is optional Voice function digital voice The CLM920 TD3 suppo...

Page 12: ...dows Vista Windows 7 Windows 10 Windows CE 5 0 6 0 7 0 Linux 2 6 or higher Android 2 3 4 0 4 2 4 4 5 0 6 0 7 1 etc Hardware reset interface Used to reset the module low effective UART serial interface...

Page 13: ...ht mode control Transmit power LTE Class 3 23dBm 2dB UMTS Class 3 24dBm 1 3dB GSM GPRS Class 4 33dBm 2dB GSM850 GSM900 Class 1 30dBm 2dB DCS1800 PCS1900 Data service GSM EDGE GPRS DL 85 6kbps UL 85 6k...

Page 14: ...40 C to 85 C Storage temperature 40 C to 85 C Humidity RH5 RH95 Module function distinction On the label paper M stands for the main set D takes the table diversity and G stands for GPS When the tempe...

Page 15: ...Module Hardware Usage Guide Shanghai Yuge Information Technology co LTD 15 The functional block diagram of the CLM920 TD3 LCC module is shown below Figure 2 1 Functional block diagram of the CLM920 T...

Page 16: ...inly describes the interface definition and application of this module Contains the following sections 144 pin pin definition map Interface definition Power interface USB interface USIM interface UART...

Page 17: ...1 144 pin LCC interface Figure 3 1 LCC module interface definition 3 2 2 Interface definition The CLM920_TD3 module interface is an LCC interface module The module interface is defined as shown in th...

Page 18: ...RESERVED 24 PCM_IN 25 PCM_OUT 26 PCM_SYNC 27 PCM_CLK 28 SDC2_DATA3 29 SDC2_DATA2 30 SDC2_DATA1 31 SDC2_DATA0 32 SDC2_CLK 33 SDC2_CMD 34 VDD_SDIO 35 ANT_DIV 36 GND 37 SPI_CS_N I2S_D1 38 SPI_MOSI I2S_W...

Page 19: ...D 87 GND 88 GND 89 GND 90 GND 91 GND 92 GND 93 GND 94 GND 95 GND 96 GND 97 GND 98 GND 99 GND 100 GND 101 GND 102 GND 103 GND 104 GND 105 GND 106 GND 107 GND 108 GND 109 GND 110 GND 111 GND 112 GND 113...

Page 20: ...Two way input and output PI power input PO Power Output AI Analog input AO Analog output DI Digital input DO Digital output OD Leaky open circuit Table 3 3 Pin description Power supply Pin Pin definit...

Page 21: ...sitive signal 90 differential impedance 70 USB_D IO USB bus differential negative signal 90 differential impedance UART interface main serial port Pin Pin definition IO Functional description Remarks...

Page 22: ...8V or 3V USIM card 15 USIM_DATA IO USIM card data 16 USIM_CLK DO USIM card clock 17 USIM_RST DO USIM card reset GPIO pin Pin Pin definition IO Functional description Remarks 1 WAKEUP_IN DI Sleep mode...

Page 23: ...lease keep it floating when not in use 27 PCM_CLK IO PCM clock pulse please keep it floating when not in use SPI interface Pin Pin definition IO Functional description Remarks 37 SPI_CS_N DO SPI chip...

Page 24: ...tic impedance please keep it floating when not in use 49 ANT_MAIN IO Main antenna 50 characteristic impedance WLAN interface Pin Pin definition IO Functional description Remarks 127 PM_ENABLE DO Power...

Page 25: ...A IO SGMII MDIO data 1 8V 2 85 voltage domain 122 SGMII_MCLK DO SGMII MDIO clock 1 8V 2 85 voltage domain 128 USIM2_VDD PO SGMII_MDATA pull up power supply 1 8V 2 85 voltage domain 123 SGMII_TX_M AO S...

Page 26: ...1 default Mode 2 GPIO Mo de 3 Functional description Whether openLinux can be opened 1 WAKEUP_IN WAKEUP_IN GPIO_25 NO 2 AP_READY AP_READY GPIO_10 NO 3 GPIO_1 GPIO_1 GPIO_42 NO 4 W_DISABLE W_DISABLE GP...

Page 27: ...SDC2_CLK SDC2_CLK 33 SDC2_CMD SDC2_CMD 34 VDD_SDIO VDD_SDIO 37 SPI_CS_N SPI_CS_N GPIO_22 SPI NO 38 SPI_MOSI SPI_MOSI GPIO_20 NO 39 SPI_MISO SPI_MISO GPIO_21 NO 40 SPI_CLK SPI_CLK GPIO_23 NO 41 I2C_SCL...

Page 28: ..._PWR PO SIM power supply 0 1 8V 2 85V 1 98 3 3V 7 VDD_EXT PO Output power 1 8V 34 VDD_SDIO PO Output power 1 8V 2 85V 8 9 10 19 22 36 46 4 8 50 51 52 53 54 56 72 85 112 GND Ground 0 The CLM920 TD3 mod...

Page 29: ...ufficient two 470uF 6 3V tantalum capacitors can be connected in parallel with the power input and then 10pF 33pF 0 1uF 1uF ceramic capacitors can be connected Figure 3 3 VBAT power supply 3 3 2 Power...

Page 30: ...vervoltages it is recommended to connect a 5 1V 500mW Zener diode to the VBAT pin of the module It is recommended to add 3 ceramic capacitors 33pF 10pF 100nF to the VBAT pin and place them near the VB...

Page 31: ...judge whether the module is powered on VDD_EXT can also be used as an external power supply such as a level shifting chip 3 4 Switching machine reset mode 3 4 1 Boot The 21 pin of the CLM920 TD3 modu...

Page 32: ...atus 22 ms Ton usb Boot time according to usb status 10 s Ton uart Boot time according to uart status 6 s VIH PWRKEY input high level 0 6 0 8 1 8 V VIL PWRKEY input low level 0 3 0 0 5 V It is recomme...

Page 33: ...0 signal of the CLM920 TD3 module is the RESET reset pin When the application detects a module error and the software does not respond the module can be reset The module can be reset by pulling the pi...

Page 34: ...M920 TD3 module supports AT command reset and the AT command is at cfun 1 1 to restart the module Detailed instructions for viewing the CLM920 TD3 AT instruction set manual 3 5 USB interface The USB i...

Page 35: ...n of the data lines differential traces and control impedance of 90 In order to improve the antistatic performance of the USB interface it is recommended to add an ESD protection device on the data li...

Page 36: ...baud rate the default is 115200bps The UART interface is defined as follows Table 3 10 UART serial port signal definition Pin Signal name I O Description parameter Level value V Rem arks Min Typical...

Page 37: ...n refer to the following serial port design Figure 3 13 UART serial port design The serial port of the module is TTL 1 8V level If the serial port needs to be connected to the MCU of 3 3V level it is...

Page 38: ...n VIH 1 2 1 8 2 VIL 0 3 0 6 12 DBG_TXD DO UART data transmission VOH 1 35 1 8 2 VOL 0 0 45 3 6 3 RI and DTR interface The CLM920 TD3 module supports the serial sleep wake up function and the RI pin ca...

Page 39: ...3 12 SIM card signal definition Pin Signal name I O Descripti on Para meter Level value V Remarks Min Typical Max 13 USIM_ DET DI USIM card detection VIH 1 6 1 8 2 This pin signal is internally pulle...

Page 40: ...circuit is susceptible to radio frequency interference and does not recognize or drop the card Therefore the card slot should be placed as far as possible from the RF radiation of the antenna The car...

Page 41: ...ertion UIM_DET is high 2 AT HOSCFG 1 0 low SIM card insertion UIM_DET is low Figure 3 17 Hot swap detection of the USIM card It is recommended to add a diode protection next to the UIM_DET pin of the...

Page 42: ...When the WAKEUP_IN signal is pulled low the host can wake up the module AP_READY this feature is under development The AP_READY pin can be used by the module to detect if the host is woken up and can...

Page 43: ...gn is as follows Figure 3 18 Network indicator circuit diagram The brightness of the network indicator can be adjusted by adjusting the current limiting resistor R The current can be adjusted up to 40...

Page 44: ...CM_SYNC of 8kHZ and PCM_CLK of 2048kHZ Table 3 18 PCM pin definition Pin Signal name I O Description Para meter Level value V Rem arks Min Typical Max 24 PCM_IN DI PCM data input VIH 1 2 1 8 2 VIL 0 3...

Page 45: ...ming diagram PCM to analog voice recommendation circuit is as follows Figure 3 21 PCM to analog voice map 3 12 I2C bus CLM920 TD3 module provides a set of hardware bidirectional serial bus I2C interfa...

Page 46: ...as follows Figure 3 22 I2C interface reference circuit diagram 3 13 SDIO interface CLM920 TD3 module provides one 4 bit SD MMC interface supports 1 8V 2 95V two voltage SD cards clock frequency up to...

Page 47: ...x 0 3 2 95V voltage domain VIL 0 3 0 25 VDD_Px 2 95V voltage domain 29 SDC2_ D2 IO SDIO bus DATA2 VOH 1 35 1 8 2 2 95V voltage domain VOL 0 0 45 1 8V voltage domain VIH 1 27 1 8 2 1 8V voltage domain...

Page 48: ...tage domain VIL 0 3 0 25 VDD_Px 2 95V voltage domain 31 SDC2_ D0 IO SDIO bus DATA0 VOH 1 35 1 8 2 1 8V voltage domain VOL 0 0 45 1 8V voltage domain VIH 1 27 1 8 2 1 8V voltage domain VIL 0 3 0 6 1 8V...

Page 49: ...n VIH 1 27 1 8 2 1 8V voltage domain VIL 0 3 0 6 1 8V voltage domain VOH 0 75 VDD_Px 2 95 VDD_Px 2 95V voltage domain VOL 0 0 125 VDD_Px 2 95V voltage domain VIH 0 625 VDD_Px 2 95 VDD_Px 0 3 2 95V vol...

Page 50: ...Z and the trace is preferably controlled by 50 ohm impedance The length of the signal line should be less than 25mm The spacing of the signal lines should be 2 times the line width and cover the groun...

Page 51: ...data output VOH 1 35 1 8 2 Reuse I2S_WS VOL 0 0 45 39 SPI_MISO DI SPIO data input VIH 1 2 1 8 2 Multiplexing I2S_D0 VIL 0 3 0 6 40 SPI_CLK DO SPI clock VOH 1 35 1 8 2 Multiplexing I2S_CLK VOL 0 0 45...

Page 52: ...gure 3 24 I2S to analog voice map 3 15 MCLK interface The CLM920 TD3 module provides one MCLK and provides a 12 288M clock output This interface is mainly used to connect the MCLK of the CODEC chip Th...

Page 53: ...C1_CLK WLAN clock DO Keep empty when not in use 134 SDC1_CMD WLAN command IO Keep empty when not in use 136 WLAN_EN WLAN enable DO Keep empty when not in use 118 WLAN_SLP_CLK WLAN sleep clock DO Keep...

Page 54: ...h as RF analog signals and noise signals such as clocks and DCDCs The SDC1_CLK signal line needs to be placed close to the module to place 15 24 termination matching resistor the SDC1_CLK pin to resis...

Page 55: ...omain 120 EPH_INT_N Ethernet PHY interrupt DI 1 8 voltage domain 121 SGMII_MDATA SGMII MDIO data IO 1 8V 2 85 voltage domain 122 SGMII_MCLK SGMII MDIO clock DO 1 8V 2 85 voltage domain 128 USIM2_VDD S...

Page 56: ...et PHY chip AR8033 reference design as shown below Figure 3 27 SGMII interface and Ethernet PHY core AR8033 reference design 3 18 ADC interface The CLM920 TD3 provides two analog to digital converter...

Page 57: ...gnal can be enhanced by adding a diversity antenna and a GNSS antenna interface is used for GPS Beidou GLONASS and GALILEO signal reception and can provide a positioning solution for the user Three wa...

Page 58: ...ails please refer to the CLM920 TD3 AT command set manual In order to facilitate the debugging of the antenna it is necessary to add a type matching circuit to the main board and take a 50 ohm impedan...

Page 59: ...d routing the antenna factory debugs and optimizes the matching device parameter values The motherboard C1 C2 C3 C4 C5 C6 defaults to 100pF L1 L2 L3 L4 L5 L6 defaults to empty In order to prevent stat...

Page 60: ...led at 50 The impedance of the RF signal line is determined by the dielectric constant of the material the trace width W the ground clearance S and the height of the reference ground plane H Please us...

Page 61: ...er PCB microstrip transmission line structure 3 19 5 RF connector size If the RF connector is used the antenna connector must use a coaxial connector with a 50 ohm characteristic impedance Hirose s UF...

Page 62: ...ogy co LTD 62 Figure 3 36 Antenna connector matching plug diagram Table 3 29 Main parameters of the RF connector Rated condition Environmental conditions Frequency Range DC to 6GHZ 40 C to 85 C Charac...

Page 63: ...arameters of GNSS Parameter Description Min Typical Max unit GPS L1 frequency Center frequency 1575MHz 1574 4 1576 4 MHz GLONASS frequency Center frequency 1601 7MHz 1597 5 1605 9 MHz BeiDou frequency...

Page 64: ...z FDD LTE B12 699MHz 716MHz 729MHz 746MHz FDD LTE B13 777MHz 787MHz 746MHz 756MHz FDD LTE B17 704MHz 716MHz 734MHz 746MHz FDD LTE B25 1850MHz 1915MHz 1930MHz 1995MHz FDD LTE B26 814MHz 849MHz 859MHz 8...

Page 65: ...G receiving sensitivity and transmit power test indicators are as follows Table 4 4 2G3G RF indicators Mode Uplink Download Power Receiving sensitivity GSM 850 824MHz 849MHz 869MHz 894MHz 33 2dBm 108d...

Page 66: ...7 LTE B25 FDD QPSK pass 95 93 5 10MHz 97 96 LTE B26 FDD QPSK pass 95 94 5 10MHz 98 97 LTE B28 FDD QPSK pass 95 95 5 10MHz 99 98 LTE B66 FDD QPSK pass 95 96 5 10MHz 96 95 LTE B40 TDD QPSK pass 95 97 10...

Page 67: ...GSM1800 2 5 1 4dbi 40 26 102 B1 FDD 2 5 1 4dbi 40 19 94 B2 FDD 2 5 1 4dbi 40 19 92 B3 FDD 2 5 1 4dbi 40 19 91 B4 FDD 2 5 1 4dbi 40 19 94 B5 FDD 2 5 1 4dbi 40 19 94 B7 FDD 2 5 1 4dbi 40 19 92 B8 FDD 2...

Page 68: ...Bi 20DB 4 7 Power consumption characteristics Table 4 9 Sleep and idle power consumption of the three major operators GNSS off Operator System condition mode Current consumption mA CMCC GSM GPS off no...

Page 69: ...ower level Current consumption mA EGSM900 1 receive 4 send 5 280 DCS1800 1 receive 4 send 0 190 EGSM900 1 receive 4 send 5 480 DCS1800 1 receive 4 send 0 460 Table 4 12 EDGE Data Transmission Power Co...

Page 70: ...s 610 20Mbps 650 LTE FDD B2 5Mbps 560 10Mbps 580 20Mbps 600 LTE FDD B3 5Mbps 570 10Mbps 590 20Mbps 660 LTE FDD B5 5Mbps 540 10Mbps 560 LTE FDD B7 5Mbps 585 10Mbps 620 20Mbps 680 LTE FDD B8 5Mbps 560 1...

Page 71: ...CLM920 TD3 LTE Module Hardware Usage Guide Shanghai Yuge Information Technology co LTD 71 20Mbps 650 LTE TDD B40 5Mbps 330 10Mbps 335 20Mbps 370 LTE TDD B41 5Mbps 320 10Mbps 329 20Mbps 360...

Page 72: ...xtreme working temperature 40 C 85 C Storage temperature 40 C 85 C 5 3 Module IO level CLM920 TD3 module IO level is as follows Table 5 2 Electrical Characteristics of CLM920 TD3 Module Parameter Para...

Page 73: ...clamp voltage VCL Clamping Voltage is less than 12V and the peak power PPP Peak Pulse Power is not less than 100W The PCB layout of the protective device should be as close as possible to the V line...

Page 74: ...hock High temperature 85 C Low temperature 40 C Temperature change time 30s Working mode no packaging no Power on do not boot Test duration 100 Cycles 15min 15min cycle JESD22 A106 B Visual inspection...

Page 75: ...nical properties 6 1 Chapter overview Exterior Module mechanical size 6 2 Exterior The CLM920 TD3 module is a PCBA with a single sided layout The appearance of the module is as follows Figure 6 1 Appe...

Page 76: ...CLM920 TD3 LTE Module Hardware Usage Guide Shanghai Yuge Information Technology co LTD 76 The figure below shows the bottom view size of the module Figure 6 3 Bottom view of the module unit mm...

Page 77: ...CLM920 TD3 LTE Module Hardware Usage Guide Shanghai Yuge Information Technology co LTD 77 Module recommended package Figure 6 4 Recommended module package unit mm...

Page 78: ...0 the factory can complete the patch within 72 hours and the module can directly perform reflow soldering or other high temperature process If the module is in other conditions it needs to be baked be...

Page 79: ...e curve is shown below Figure 7 1 Reflow soldering temperature graph Table 7 1 Reflow process parameter table Warm zone Time Key parameter Preheating zone 40 165 Heating rate 1 s 3 s Temperature zone...

Page 80: ...ror Rate CCC China Compulsory Certification CDMA Code Division Multiple Access CE European Conformity CSD Circuit Switched Data CTS Clear to Send DC Direct Current DTR Data Terminal Ready DL Down Link...

Page 81: ...Radio Frequency RoHS Restriction of the Use of Certain Hazardous Substances SMS Short Message Service TIS Total Isotropic Sensitivity TVS Transient Voltage Suppressor TX Transmitting Direction UART Un...

Page 82: ...GMSK CS 4 21 4kb s time slot 85 6kb s GMSK Table 8 4 Maximum EDGE Rate GPRS coding scheme Max data rata 4 slots Modulation type MCS 1 8 8kb s time slot 35 2kb s GMSK MCS 2 11 2kb s time slot 44 8kb s...

Page 83: ...AM QPSK Category 11 0 9Mbps QPSK Category 12 1 8Mbps QPSK Category 13 17 6Mbps 64QAM Category 14 21 1Mbps 64QAM Category 15 23 4Mbps 16QAM Category 16 28Mbps 16QAM Category 17 23 4Mbps 64QAM Category...

Page 84: ...reless devices is prohibited or the use of the device causes interference and security of the electronic device turn off the wireless device Because the terminal will send and receive RF signals when...

Page 85: ...the airline s regulations and regulations regarding the use of wireless equipment Before taking off turn off the wireless device to prevent wireless signals from interfering with aircraft control sign...

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