CLM920_AC3 Module Hardware Usage Guide
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Table 3-22 Wireless connection pin definition
Pin
Name
I/O
Description
28
WLAN_WAKE_HOST
DO
WLAN wake up HOST
29
WLAN_CLK
DO
WLAN SDIO clock
30
WLAN_CMD
IO
WLAN SDIO command
31
SDC_DATA0
IO
WLAN SDIO bus DATA0
32
SDC_DATA1
IO
WLAN SDIO bus DATA1
33
SDC_DATA2
IO
WLAN SDIO bus DATA2
34
SDC_DATA3
IO
WLAN SDIO bus DATA3
37
WLAN_CLK_EN
DO
External clock enable control pin
38
WLAN_CLK_26M
DO
26MHZ clock
39
WLAN_PDN
DO
Power saving mode control
40
WLAN_DC_EN
DO
DCDC enable control pin
The SDIO bus speed is fast, and the Layout trace must conform to the SDIO3.0
specification.
The length of the signal line should be less than 50mm, the spacing of the signal line
should be 2 times the line width and cover the ground and be as far away as possible
from other possible interference lines;
The WLAN_CLK signal line is connected in series with a matching resistor on the
module end, and the trace needs to be processed in the package.
。
3.13 ADC interface
The CLM920 AC3 provides two analog-to-digital converter interfaces to read the voltage
value. The input voltage of the ADC interface cannot exceed 1.3V. It is recommended that the
ADC pin be input with a voltage divider circuit.
Table 3-23 ADC Pin Definitions
Pin
Name
Description
Level value (V)
Remarks
Min
Typical Max
44
ADC1
Analog to digital
0.3
1.3V
ADC
