2-3
IM 703155-01E
Functional Description
2
Block Diagram
10 MHz REF IN
10 MHz REF OUT
CLOCK IN
CLOCK OUT
START IN
READY OUT
Waveform
Memory
64 M/128 M
Points
DAC
Matrix Operation
LPF
6 M/30 M/
100 M/THRU
Gain/Phase/
Gain Ratio/Quadrature
Differential
Offset
Common
Offset
DAC
DAC
DAC
DAC
DAC
Differential
Offset
Common
Offset
EVENT OUT 0
EVENT OUT 1
IQ DIGITAL OUT
CFD
ETHERNET
CPU
HDD
USB
SERIAL
(RS-232)
VIDEO
OUT
I
I
Q
Q
Sequence
Controller
AWGN
AWGN
LPF
6 M/30 M/
100 M/THRU
Trigger Out
Trigger In
Trigger
Sampling
Clock
Sequence Trigger
Controller
Trigger signal
OUT1-OUT4
SEQ Trigger
SMPLG
IN
Differential
Offset
Common
Offset
DAC
DAC
DAC
DAC
Differential
Offset
Common
Offset
I
I
Q
Q
I,Q Signal
from OUT1-OUT4
/AT Option
To /AT Option block
ANALOG SUM
EXT IN
Q
I
TRIG IN
TRIG OUT
SMPLG
OUT
Control & Interface
Clock Generator
OUT3
OUT1
OUT2
OUT4
For a description of the signal flow in the block diagram, see the explanation on the next
page.
2.2 System Configuration and Block Diagram
