1.7 BERT Module
AQ2200-601 10 Gbit/s BERT Module
External clock signal input terminal
If you want to operate the BERT module
with an external clock signal at a rate of
10 Gbit/s, without using the internal SG,
apply a 10 Gbit/s clock signal to this
terminal. This clock is used not only for the
PPG, but also for the reference clock signal
to operate the CDR function of the ED.
Data output terminal (to the optical modulator)
Non-inverted data output terminal.
Used when this module is combined
with an optical modulator module.
Lock lever
Used when installing and
uninstalling the module.
Lock lever release button
Releases the lock lever.
Signal output indication lamp
This lamp shows the status of the PPG signal
output.The lamp is lit when the output is on.
Signal output ON/OFF key
Turns all of the PPG output terminals on or off at once.
Each time this key is pressed, signal output switches
between on and off.
Trigger signal output terminal
Transmits one of the following
trigger signals.
(For details, see section 1.6 in
IM 735101-03E.)
• Clock trigger (1/16 or 1/64)
• Pattern trigger
• Error trigger
Data input 2 terminal
ED data input terminal. This
terminal requires a clock signal to
be applied to the clock signal input
terminal.
Data input 1 terminal
ED data input terminal. Because
this terminal has a built-in CDR
(clock and data recovery), it does
not require clock input.
Fixing screw
Inverted clock signal output terminal
Transmits the 10 GHz inverted clock
signal. When output is on, this
terminal transmits the inverted clock
signal of the 10 GHz band.
Non-inverted clock signal
output terminal
Transmits the 10 GHz non-inverted
clock signal. When output is on, this
terminal transmits the non-inverted
clock signal of the 10 GHz band.
Inverted data output terminal
When output is on, this terminal
transmits the 10 Gbit/s inverted data.
Non-inverted data output terminal
When output is on, this terminal
transmits the 10 Gbit/s non-inverted
data.
External synchronization signal
input terminal
If you want to synchronize the BERT
module with an external clock signal
and have the module generate a PPG
signal, without using the internal SG,
apply a reference signal that has a
frequency that is 1/16 or 1/64 of the
10 Gbit/s rate to this terminal. This
clock is used not only for the PPG, but
also for the clock signal to operate the
CDR function of the ED.
Fixing screw
When you install the module, tighten
the screws to fix the module in place.
Clock signal input terminal
ED clock signal input terminal.
When you apply a signal to the
data input 2 terminal, apply a clock
signal to the clock signal input
terminal. Adjust the phase by using
an instrument such as an external
phase shifter.
Note
• When using the external synchronization input terminal and the data input 1 terminal:
If the signal applied to the ED’s data input 1 terminal is not synchronized with the PPG, adjust
the settings so that the frequency 16 or 64 times larger than the reference signal to be applied
to the external synchronization input terminal is within ±100 ppm of the input data rate.
• When using the external clock input terminal and the data input 1 terminal:
If the signal applied to the ED’s data input 1 terminal is not synchronized with the PPG,
adjust the settings so that the frequency 16 or 64 times larger than the reference signal to
be applied to the external clock input terminal is within ±100 ppm of the input data rate.
1-21
IM 735101-01EN
Component Names and Functions
1
2
3
4
5
Index
