2-2
IM 765501-01E
Block Diagram
DUT: Device Under Test
CPU
VFD
KEY
EXT I/O
RS-232
GP-IB
USB
ETHER
(option)
Analog
control
Limiter DAC
ADC
Source DAC
Limiter
control
circuit
Current sense
amplifier
Voltage sense amplifier
LO
HI
DUT
Vo
Io
Voltage Vo that appears across output terminals HI and LO is converted to normalized
voltage by a differential amplifier (voltage sense amplifier) that has different gains for
different voltage ranges. In addition, current Io that flows through output terminals HI
and LO is converted to normalized voltage by different shunt resistors and differential
amplifiers (current sense amplifiers) for different current ranges.
The analog section consists of the source block, limiter block, and measurement block.
The source block controls the voltage sense amplifier or the current sense amplifier so
that its output is equal to the source DAC output, and delivers the specified source value
across HI and LO. Two D/A converters are used in the source DAC to achieve a 5.5-
digit resolution.
The limiter control circuit in the limiter block controls the output across HI and LO so that it is
equal to the specified limiter value when the output from the voltage sense amplifier or
current sense amplifier exceeds the specified limiter value. When generating voltage, the
output from the current sense amplifier is compared with the limiter value; when generating
current, the output from the voltage sense amplifier is compared with the limiter value.
The measurement block measures the output from the voltage sense amplifier or current
sense amplifier. In addition, if the auto zero function is enabled, the internal zero
reference is measured every measurement cycle (measurement operation), and the
offset drift of the measurement pre-amplifier and A/D converter is cancelled while
measurements proceed. A feedback pulse width modulation (an integration type) is
employed for the A/D converter (ADC).
The analog control section transfers data to the D/A converter (DAC), controls various
switches, controls the width measurement of the pulse transferred from the A/D
converter, and so on. To achieve high-speed sweep of 100
µ
s steps, a high-speed
photocoupler is employed for the transferring of data to the source DAC.
The display employs a 256
×
64 dot VFD
*
to improve the visibility.
The GS610 comes with GP-IB and RS-232 interfaces that provide compatibility with
conventional systems as well as a USB port that is convenient for writing to or reading
data from a PC. An Ethernet port is also provided as an option if you wish to use the
existing network for data communication.
* Vacuum Fluorescent Display
2.1 System Configuration and Block Diagram