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Hardware interrupt
Description
Assignment
Hardware gate opening
Hardware interrupt by edge 0-1 exclusively at HW gate
channel 3
n
enabled: Process interrupt by edge 0-1 exclusively at
HW gate channel 3 with open SW gate
n
disabled: no hardware interrupt
disabled
Hardware gate closing
Hardware interrupt by edge 1-0 exclusively at HW gate
channel 3
n
enabled: Process interrupt by edge 1-0 exclusively at
HW gate channel 3 with open SW gate
n
disabled: no hardware interrupt
disabled
On reaching comparator
Hardware interrupt on reaching
comparator
n
enabled: Hardware interrupt when comparator is trig-
gered, can be configured via
‘Characteristics of the
output’
n
disabled: no hardware interrupt
disabled
Overflow
Hardware interrupt overflow
n
enabled: Hardware interrupt on overflow the upper
counter limit
n
disabled: no hardware interrupt
disabled
Underflow
Hardware interrupt on underrun
n
enabled: Hardware interrupt on underflow the lower
counter limit
n
disabled: no hardware interrupt
disabled
12.6.6
Frequency measurement
12.6.6.1
Overview
n
4 channels
n
Sub module
‘Counter’
n
Chap. 5.7 ‘Frequency measurement’ page 148
12.6.6.2
Parametrization in SPEED7 Studio
12.6.6.2.1
‘I/O addresses’
Sub module
Input address
Access
Assignment
Count
816
DINT
Channel 0: Counter value / Frequency value
820
DINT
Channel 1: Counter value / Frequency value
824
DINT
Channel 2: Counter value / Frequency value
828
DINT
Channel 3: Counter value / Frequency value
VIPA System SLIO
Configuration with VIPA SPEED7 Studio
Deployment I/O periphery > Frequency measurement
HB300 | CPU | 013-CCF0R00 | en | 19-30
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