Yamaha RX-V675, Service Manual

Page: 131 / 182

A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
131
DIGITAL 5/8
RX-V675/HTR-6066/RX-A730/TSR-6750
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked ⚠ and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
3.3 3.3
2.0
3.3
5.5
1.5
1.5
0.6 0 1.5 1.5
1.5 3.3 3.3
3.3
1.5 (U, C models)
3.3
M T _ N _ Z 2
M T _ S W
M T _ Z 2
M T _ S B
M T _ 5 C H
232C_MOSI
A[15] A[17]
D[13]
A[20]
A[3]
EX_MOSI
A[5]
FLD_N_CS
A[19]
D B G _ C N V S S
DBG_CNVSS
D[10]
A[8]
D[12] D[14]
A[6]
M C P U _ N _ R S T
K Y _ A D 2
D B G _ S C K
D B G _ B U S Y D B G _ E P M
A[10] A[22] A[21]
D[11]
D B G _ S C K
A[16]
D [ 0 ]
A[9] A[2]
2 3 2 C _ D B G _ M O S I
A[14]
EX_SCK
D[8]
D [ 7 ]
D [ 3 ]
A[12]
D [ 6 ]
D[9]
D [ 2 ]
A[4]
D [ 5 ]
D [ 1 ]
HTX1_N_INT
A[18]
D [ 4 ]
D B G _ B U S Y
A[7] A[1]
D[15]
EEP_N_CS
D B G _ N _ C E
A[11]
K Y _ A D 1
A[13]
2 3 2 C _ D B G _ M I S O
D [ 8 ]
D [ 4 ]
D [ 7 ]
] 4 1 [ D ] 9 [ D
D [ 1 1 ]
D [ 2 ]
+ 3 . 3 D _ P O N
D [ 6 ]
D [ 1 2 ]
D [ 3 ]
D [ 1 5 ]
D [ 0 ]
D [ 1 ]
] 3 1 [ D ] 0 1 [ D
D [ 5 ]
D [ 1 5 ]
D [ 7 ]
D [ 1 4 ]
D [ 6 ]
D [ 1 3 ]
D [ 5 ]
D [ 4 ]
D [ 1 2 ]
D [ 3 ]
D [ 1 1 ]
D [ 1 0 ]
D [ 2 ]
D [ 9 ]
D [ 1 ]
D [ 8 ]
D [ 0 ]
A [ 1 ]
A [ 2 ]
A [ 3 ]
A [ 4 ]
A [ 5 ]
A [ 7 ]
A [ 6 ]
A [ 8 ]
A [ 1 8 ]
A [ 1 9 ]
A [ 1 1 ]
A [ 1 3 ]
A [ 1 0 ]
A [ 9 ]
A [ 2 0 ]
A [ 1 4 ]
A [ 1 2 ]
A [ 1 5 ]
A [ 1 6 ]
A [ 1 7 ]
F L A S H _ N _ C S
FLASH_N_CS
M C B U S _ N _ R D
MCBUS_N_RD
M C B U S _ N _ W R _ F L
MCBUS_N_WR_FL
A [ 2 1 ]
A [ 2 2 ]
DFF1_N_CS MCBUS_N_WR_FF
D F F 1 _ C L K
M C B U S _ N _ R D
M C B U S _ N _ W R _ F P
F P G A _ N _ C S
D B G _ E P M
F P G A _ N _ C S
L M T _ D C
L M T _ O L V
AD1_COM
VOL_RA
D F F 1 _ N _ C S
232C_MISO
TUN_SCL TUN_SDA VOL1_SCK
ACPWR_DET DAU_N_INT HRX_N_INT
VOL_RB
TUN_SCL TUN_SDA
TUN_N_RST
VOL_MOSI VOL1_SCK
W A K E U P _ I N T
WAKEUP_INT
H D M I _ P O N
H T X _ A U S E L
H A U _ N _ O E
M T _ N _ S W
M T _ N _ S W
M T _ N _ Z 2
M T _ N _ 5 C H
M T _ N _ S B
M T _ N _ 5 C H
M T _ N _ S B
N C P U _ S P I _ N _ C S
N D A C _ N _ M T
L M T _ P S 1
L M T _ P S 2
AMP_OLV
DC_PRT
PS1_PRT
L M T _ P S 2
L M T _ P S 1
L M T _ O L V
L M T _ D C
THM1
TUN_N_INT
FLD_N_RST
FLD_N_CS
FLD_SCK
FLD_MOSI
MIC_N_DET
REM_IN1 ISEL_RA ISEL_RB
KY_AD1 KY_AD2 VOL_RA VOL_RB PD_LED
FLD_PON
STBY_LED
PSW_DET
E X _ S C K
E X _ M O S I
F L D _ S C K
HDMI_SDA
F L D _ M O S I
FLD_PON
PS2_PRT
I_PRT MIC_N_DET PD_LED HSW2_N_INT HSW1_N_INT
FHDMI_N_INT
ISEL_RA ISEL_RB
2 3 2 C _ M I S O
I S O M _ C 2 3 2 I S O M _ G B D _ C 2 3 2
D S P 1 _ N _ R S T
N C P U _ P O N
EX_SCK
NCPU_AMUTE
F P G A _ N _ C F G
A D 1 _ C O M
T U N _ N _ R S T
+ 3 . 3 S _ P O N
D S P 1 _ N _ I N T
F P G A _ N _ S T A
F P G A _ C D O N E
H R T X _ N _ R S T
P R Y
V I D _ P O N
F H D M I _ N _ R S T
H S W _ N _ R S T
V D E C _ N _ R S T
D S P _ P O N
S P R Y _ Z 2 & F P
A D 2 _ C O M
AD_SEL_C AD_SEL_B AD_SEL_A AD_SEL_A AD_SEL_B AD_SEL_C
LMT_I
REM_IN1 LMT_I
HPRY
SPRY_SB&BA SPRY_Z2&FP
H P R Y
S P R Y _ S B & B A
HDMI_SCL
NCPU_SPI_MISO
NCPU_SPI_SCK
2 3 2 C _ D B G _ M I S O 2 3 2 C _ D B G _ M I S O
D S P _ S C K
D S P _ M I S O
D S P _ M O S I
N C P U _ S P I _ R D Y
TUN_N_INT
NCPU_N_RST
D I R _ N _ R S T
D I R 1 _ N _ C S
M T _ D A
SPRY_5CH VOL_MOSI PA_B_RY
EEP_MISO
D B G _ N _ C E
AD2_COM
FPGA_SCK
A D _ S E L _ B
FPGA_MOSI
A D _ S E L _ A
A D _ S E L _ C
N C P U _ V B U S D R V
+3.3D_PON DEST MCPU_N_RST VDEC_N_RST NCPU_SPI_REQ HDMI_PON HDMI_PON NCPU_SPI_RDY NCPU_SPI_MOSI NCPU_SPI_MISO FPGA_N_STA NCPU_SPI_SCK FPGA_CDONE FHDMI_N_RST FPGA_MOSI HAU_INT FPGA_SCK HSW_N_RST HRTX_N_RST HAU_N_OE HRTX_N_RST HDMI_PON HDMI_SDA HTX_AUSEL PRY HDMI_SCL FPGA_N_CFG ACPWR_DET PSW_DET
PS2_PRT
U S B _ V B U S _ P O N
PA_B_RY
HTX1_N_INT HRX_N_INT
NCPU_SPI_REQ
AMP_LMT
AMP_LMT
E E P _ N _ C S
NCPU_VBUSDRV
D F F _ F R O M _ N _ R S T
EEP_MISO
EX_MOSI
NCPU_SPI_MOSI
I R _ O U T
MODEL
USB_VBUS_PRT
USB_VBUS_PRT
MODEL DEST
DEST
USB_VBUS_PON
D S P 1 _ N _ C S
D S P 1 _ N _ S P I R D Y
NCPU_SPI_N_CS NCPU_N_RST NCPU_AMUTE NCPU_PON
P S 3 _ P R T
PS3_PRT
L M T _ P S 3
NDAC_N_MT DSP_PON MT_DA DIR_N_RST DIR1_N_CS DSP1_N_RST DSP1_N_CS DSP_SCK DSP_MOSI DSP_MISO DSP1_N_SPIRDY DIR1_N_INT DSP1_N_INT
DAU_N_INT
VID_PON
W I F I _ P O N
WIFI_PON
THM2
+ 3 . 3 S _ P O N
HDMI_PON
2 3 2 C _ D B G _ M I S O
DFF_FROM_N_RST
DFF_FROM_N_RST
D I R 1 _ N _ I N T
M C B U S _ N _ W R _ F P
M C B U S _ N _ W R _ F L
M C B U S _ N _ W R _ F F
D S P _ S C K _ A
DSP_SCK_A
THM2 THM1THM1
DC_PRT
PS1_PRT AMP_OLV
MT_5CH
MT_SB MT_Z2 MT_SW I_PRT
PS2_PRT
HP_N_DET
THM3
THM3
PS2_PRT
DV_SCLDV_SCL DV_SDADV_SDA
RM+ RM-
D S P _ S C K
RM- RM+ IR_OUT
H P _ N _ D E T
D C _ T R G 1
DC_TRG1
DV_SCL DV_SDA
DV_SDA DV_SCL
F L D _ N _ R S T
FHDMI_N_INT
MHL_VBUS_PRT
MHL_VBUS_PRT
M H L V B _ P O N
S T B Y _ L E D
HSW1_N_INT HSW2_N_INT MHLVB_PON
HAU_INT
F L D _ P O N
HTX2_AUSEL
HTX2_AUSEL
L3_DET
L3_DETL3_DET
L 3 _ D E T
DSP_PON
PRY
T
S
R
_
N
_
U
P
C
M
T
S
R
_
N
_
U
P
C
M
L M T _ P S 3
L 3 _ D E T
Z A D C _ N _ P D W N
ZADC_N_PDWN HDMI_PON
SPRY_5CH
AMP_LMT
C792
1/25
100K
R853
R785 47K
C B 7 7
n o _ u s e
1 2
1
2
11
3 4 5 6 7 8 9
10
C790
0.1/10(BJ)
C805
0.1/10(BJ)
HDMI_PON
IC80
V -
3
DGND
100K
R872
DGND
100P(CH)
C829
R780
100
K
D G N D
R 7 5 2
1 K
+3.3M
C 7 5 6
1 0 0 0 P ( B )
+ 5 A
NCPU_SPI_MISO
D G N D
R P 1 3 0 Q 3 3 1 D - T R - F
Y C 2 8 8 A 0
I C 8 5
4
VDD
2
GND
3
VOUT
1
CE/CE
R 7 5 0
1 K
R768
no_use
R804
220KX4
PRY
HDMI_SDA
1K
R815
4 . 7 K
R 8 5 8
R 8 0 0
3 3 X 4
1000P(B)
C847
+3.3S
8 5 7 Q
R L T B U 6 7 5 1 A
D N G D
R812 33X4
R850 680
1000P(B)
C836
IC75
V +
5
NCPU_SPI_RDY
IC92
V +
5
1K
R773
C 7 5 8
1 0 0 0 P ( B )
+ 3 . 3 M
0
J750
R 7 8 2
1 0 0 X 4
I C 9 1
T C 7 S H 8 6 F U
2
1
4
L751
no_use
R877 18K
C797 1/25
4 5 7 Q
R L T B U 6 7 5 1 A
R760
no_use
4 . 7 K
R 8 5 7
D750
RB521S-30TE61
Q 7 5 3
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
1 0 K
R 7 8 3
HRX_N_INT
C 8 1 5
n o _ u s e
+ 3 . 3 S
+3.3S
D G N D
DSP1_N_CS
D G N D
Q 7 5 6
A 1 5 7 6 U B T L R
D G N D
IC91
V -
3
R 7 9 4
3 3
DIR1_N_CS
R759 10K
PSW_DET
D G N D
4 7 K
R 8 2 6
R 7 7 7
1 0 0 X 4
D G N D
R817
22
+ 3 . 3 S
1000P(B)
C846
L750
BKP1005HS680-T
+3.3S
R823
33X4
C 7 6 7
1 0 0 0 P ( B )
R 8 3 6
1 0 0 K
NCPU_SPI_MOSI
R 8 6 0
1 K
R 8 8 3
4 7
+ 3 . 3 S
DGND
1000P(B)
C834
+ 3 . 3 M
DGND
10
K
R763
R807
33
I C 8 0
T C 7 S H 3 2 F U
2
1
4
C 8 2 1
n o _ u s e
C774
100P(CH)
+ 3 . 3 M
R 7 6 5
1 0 K
R822 33X4
USB_VBUS_PRT
1000P(B)
C831
C 8 2 8
n o _ u s e
D G N D
DIR1_N_INT
A [ 0 - 2 2 ]
IC92
V -
3
R 8 8 5
4 7
4 7
R 8 8 2
FPGA_N_CFG
+ 3 . 3 D S P
R 8 0 2
3 3 X 4
NCPU_SPI_REQ
+ 3 . 3 M
HSW1_N_INT
D [ 0 - 1 5 ]
R 7 5 1
9 . 1 K
C782
100P(CH)
R 8 2 9
3 3
DGND
R869 22K
100
R772
1000P(B)
C843
1000P(B)
C837
D G N D
DGND
+ 3 . 3 M
C 7 7 0
1 0 0 0 P ( B )
4 . 7 K
R 8 1 4
4 . 7 K
R 8 5 6
I C 8 3
R 5 F 6 4 1 6 M A D F E
Y F 2 5 2 A 0
1 2 3 4 5 6 7 8 9 10 1
1
12 13 14 15 16 17 18 19 20 21 22 23 24 25
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
1 5 2
1 5 3
1 5 4
1 5 5
1 5 6
1 5 7
1 5 8
1 5 9
1 6 0
1 6 1
1 6 2
1 6 3
1 6 4
1 6 5
1 6 6
1 6 7
1 6 8
1 6 9
1 7 0
1 7 1
1 7 2
1 7 3
1 7 4
1 7 5
1 7 6
26 27 28 29 30 31
7 0
7 1
7 2
7 3
7 4
7 5
7 6 1 4 5
1 4 6
1 4 7
1 4 8
1 4 9
1 5 0
1 5 1
32
101 102 103 104 105 106 107
33 34 35 36
7 7
7 8
7 9
8 0
100
97 98 99
1 4 4
1 4 1
1 4 2
1 4 3
37 38 39 40 41 42 43 44
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
96 95 94 93 92 91 90 89
1 4 0
1 3 9
1 3 8
1 3 7
1 3 6
1 3 5
1 3 4
1 3 3
1 0 0
R 7 7 8
C763
0.1/10(BJ)
T P 8 5 9
C794
1/25
C 7 8 3
4 . 7 / 6 . 3
R766 10K
DGND
R806
33
4 7
R 8 8 7
0 . 1 / 1 0 ( B J )
C 7 7 9
10K
R880
D G N D
C776
1000P(B)
NCPU_VBUSDRV
R764
20K
R808
220KX4
DSP_SCK DSP1_N_INT
4 7 0
R 8 4 1
R876 10K
M C B U S _ N _ R D
R827
10
D G N D
R874 68K
DV_SCL
DSP_MOSI
NCPU_AMUTE
F P G A _ N _ C S
R 8 0 1
3 3 X 4
C B 8 5
n o _ u s e
1
2
1 2
1 1
3
4
5
6
7
8
9
1 0
DGND
DIR_N_RST
+ 5 . 5 V
R 8 1 8
1 M
+ 3 . 3 S
R871
33
IC75
V -
3
1000P(B)
C809
+ 5 . 5 V
R 8 4 6
2 . 2 K
HAU_INT
100K
R852
C793
1/25
C798
4.7/6.3
D G N D
NCPU_PON
D G N D
C 7 6 6
1 0 0 0 P ( B )
R878 10K
+ 3 . 3 M
FPGA_CDONE
C 8 1 0
n o _ u s e
R786 47K
FPGA_MOSI
+ 3 . 3 M
+ 3 . 3 S
IC93
4
DGND
C 8 1 8
n o _ u s e
3 3
R 8 3 4
R 7 5 5
1 0 K
C 8 1 6
n o _ u s e
+3.3S
HDMI_PON
R 8 9 0
3 3
Q 7 5 9
A 1 5 7 6 U B T L R
HTX1_N_INT
D G N D
D G N D
IC79
TC74VHC273FT
1
D I R
2
A 1
3
A 2
4
A 3
5
A 4
6
7
8
9
10 1
11
21
31
41
5
16
B 3
17
B 2
18
B 1
19
G
20
V C C
D G N D
DSP1_N_RST
R809 33X4
100K
R855
C 7 6 0
1 0 0 0 P ( B )
C 8 2 5
n o _ u s e
C 7 7 2
0 . 1 / 1 0 ( B J )
100K
R854
C 8 2 2
n o _ u s e
C777
1000P(B)
IC91
V +
5
TP754
D G N D
+ 3 . 3 M
C 7 5 9
1 0 0 0 P ( B )
R P 1 3 0 Q 3 3 1 D - T R - F
Y C 2 8 8 A 0
I C 8 4
4
VDD
2
GND
3
VOUT
1
CE/CE
D G N D
C773
100P(CH)
3 3
R 8 4 0
C 7 6 8
0 . 1 / 1 0 ( B J )
1000P(B)
C786
C780
1/25
C 7 6 2
1 0 0 0 P ( B )
VDEC_N_RST
D G N D
+ 3 . 3 M
C803
4.7/6.3
FPGA_SCK
C778
0.1/10(BJ)
1000P(B)
C840
NDAC_N_MT
C 7 5 5
1 0 0 0 P ( B )
D G N D
1K
R770
D G N D
R824 33X4
DGND
R 8 6 1
4 7 0
C807
no_use
R 7 9 7
3 3
+ 3 . 3 S
R805 33X4
+5.5V
Q 7 5 1
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
+ 3 . 3 M
D G N D
+ 3 . 3 M
R888 100X4
C 7 5 2
1 0 0 0 P ( B )
C 8 2 3
n o _ u s e
C769
33/10
C795
1/25
100K
R784
+3.3S
R 8 6 3
4 7 0
R762
no_use
R 7 9 2
2 2 0 K X 4
C 7 6 5
1 0 0 0 P ( B )
1000P(B)
C781
+ 3 . 3 S
+ 3 . 3 M
1000P(B)
C808
+ 3 . 3 M
R873
100K
C B 7 5
n o _ u s e
1 2 3 4
+3.3M
+ 5 . 5 V
R879
100K
7 5 7 Q
R L T B U 6 7 5 1 A
DGND
100 R790
1000P(B)
C844
R 8 8 9
3 3
C 8 2 6
n o _ u s e
D G N D
FPGA_N_STA HAU_N_OE
R894
10K
C B 8 4
5 2 0 4 5
V Q 0 4 7 2 0
1
2
3
4
5
6
7
8
9
+ 3 . 3 M
0.1/10(BJ)
C785
Q 7 5 0
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
+ 3 . 3 D S P
C 8 1 2
n o _ u s e
C 8 0 1
0 . 1 / 1 0 ( B J )
I C 9 3
T C 7 W H 1 2 6 F U ( T E 1 2
5 3
7
+ 3 . 3 D S P
C 8 2 4
n o _ u s e
C 8 1 1
n o _ u s e
R810
33
+ 3 . 3 M
C796
0.1/10(BJ)
IC80
V +
5
+ 3 . 3 D S P
+3.3M
100P(CH)
C830
1000P(B)
C838
1000P(B)
C842
R 8 6 2
4 7 0
DSP1_N_SPIRDY
R831
33
C 7 5 0
1 0 0 0 P ( B )
C 8 2 7
n o _ u s e
I C 7 6 S N 7 4 L V 4 0 5 1 A P W R
1
Y4
2
Y6
3
COM
4
Y7
5
Y5
6 7 8
9 1 0 1 1 1 2
Y3
1 3
Y0
1 4
Y1
1 5
Y2
1 6
VCC
R 7 9 6
n o _ u s e
D G N D
R866
220K
M C B U S _ N _ W R _ F P
+ 3 . 3 M
DGND
DGND
10K R87
5
FHDMI_N_RST
DGND
DSP_PON
R 7 9 9
3 3 X 4
R828
33
+ 3 . 3 M
R 7 8 8
3 3
D G N D
R881 100X4
D G N D
R821 33X4
R754
no_use
C 7 5 3
1 0 0 0 P ( B )
IC93
8
D G N D
IC77
MX29LV640EBTI-7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
24
25
26
27
28
29
30
31
32
33
3
43
53
63
73
83
9
40
41
42
43
44
45
46
47
48
R 8 9 3
n o _ u s e
R 7 9 1
2 2 0 K X 4
T P 7 5 8
DGND
4 7
R 8 8 4
C791
0.1/10(BJ)
R811
33
DGND
D G N D
C806
no_use
D G N D
C 8 1 3
n o _ u s e
1000P(B)
C848
WIFI_PON
R816
22
R 8 3 2
3 3
R 8 4 9
3 3
+ 3 . 3 M
NCPU_SPI_N_CS
R775
no_use
Q 7 5 5
A 1 5 7 6 U B T L R
T P 7 6 7
R753 10K
C 8 1 9
n o _ u s e
MCPU_N_RST
C789
0.1/10(BJ)
R819 33X4
NCPU_N_RST
X L 7 5
8 M H Z
1
2
3
R 7 9 5
n o _ u s e
NCPU_SPI_SCK
D G N D
C 7 7 5
0 . 1 / 1 0 ( B J )
R 8 3 5
3 3
C 7 6 1
1 0 0 0 P ( B )
3 3
R 8 4 2
R895 10K
DGND
R 8 4 5
2 . 2 K
D G N D
1000P(B)
C839
R 8 3 0
1 0 0 K
C 7 5 1
1 0 0 0 P ( B )
D G N D
HDMI_PON
+ 3 . 3 S
HSW_N_RST
0 . 1 / 1 0 ( B J )
C 7 8 8
R844 33X4
100P(CH)
C784
R867 100X4
+3.3D_PON
DGND
J840
no_use
DV_SDA
C 8 0 2
0 . 1 / 1 0 ( B J )
+ 5 . 5 V
3 3
R 8 4 3
IC82
R 1 E X 2 5 5 1 2 A T A 0 0 A
1
S
2
Q
3
W
4
V S S
5
D
6
C
7
H O L D
8
V C C
HTX_AUSEL HRTX_N_RST
IC75
TC7SH08FU
2 1
4
MT_DA
R865 10K
C 7 5 7
1 0 0 0 P ( B )
D G N D
+ 3 . 3 M
HDMI_PON
C754
0.1/10(BJ)
R 8 9 6
n o _ u s e
0 . 1 / 1 0 ( B J )
C 7 8 7
R 8 4 8
4 7 0 K
Q 7 6 0
C4081UBTLR
10K R767
33
K
R776
+ 3 . 3 M
C 7 7 1
0 . 1 / 1 0 ( B J )
C 7 6 4
1 0 0 0 P ( B )
DGND
R 7 8 9
3 3
R 8 3 8
3 3 X 4
C799 1/25
USB_VBUS_PON
R 7 6 1
1 0 K
1000P(B)
C845
+ 3 . 3 M
1K
R771
1000P(B)
C841
4.7K
R774
I C 9 2
S N 7 4 L V C 1 G 1 7 D C K R
2 4
R 8 3 7
3 3 X 4
HRTX_N_RST
I C 7 8 S N 7 4 L V 4 0 5 1 A P W R
1
Y4
2
Y6
3
COM
4
Y7
5
Y5
6 7 8
9 1 0 1 1 1 2
Y3
1 3
Y0
1 4
Y1
1 5
Y2
1 6
VCC
C 8 1 4
n o _ u s e
3 3
R 8 9 7
C B 8 3
R F - H 0 2 2 T D
V G 5 1 8 3 0
R 8 3 9
3 3 X 4
ACPWR_DET
D G N D
DSP_MISO
I C 9 3
T C 7 W H 1 2 6 F U ( T E 1 2
2 6
1
1000P(B)
C835
DEST
1K
R769
R870
3.3K
R 7 9 3
3 3
1000P(B)
C832
R 7 9 8
3 3 X 4
D G N D
+ 3 . 3 M
TP752
C 8 2 0
n o _ u s e
IC81
TC74VHC273FT
1
D I R
2
A 1
3
A 2
4
A 3
5
A 4
6
7
8
9
10 11
12
13
14
15
16
B 3
17
B 2
18
B 1
19
G
20
V C C
4 . 7 K
R 8 5 9
R813 33X4
R 8 8 6
4 7
+ 3 . 3 S
C 8 1 7
n o _ u s e
D G N D
R 7 7 9
1 0 0 X 4
DGND
R 7 8 1
1 0 0 X 4
1K
R820
D G N D
+ 3 . 3 M
HDMI_SCL
+ 3 . 3 M
Q 7 5 2
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2 C 2
C 1
R868 100X4
3 3
R 8 9 8
3 3
R 8 9 9
R 8 4 7
1 0 K
D G N D
R 7 5 7
1 8 0
DSP_SCK_A
R 8 5 1
4 7 K
+3.3M
R 8 3 3
n o _ u s e
DGND
R 8 2 5
1 M
C B 7 8
P H I
V B 3 9 0 8 0
1 2 3 4 5 6 7 8 9
10 11 12
C B 8 0
P H I
V B 3 9 0 6 0
1 2 3 4 5 6 7 8 9
10
C B 7 6
5 2 0 4 4
V Q 0 4 4 8 0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18
C B 8 2
5 2 0 4 5
V P 0 8 2 9 0
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 1
9
20 21 22 23 24 25
R 9 0 3
4 7 0 K
R904 680
3 3 0
R 9 0 2
Q 7 6 3
A 1 5 7 6 U B T L R
+3.3S
DGND
ADCVBS ADY ADPb ADPr
+ 3 . 3 V
D G N D
IC87
V +
5
IC87
V -
3
I C 8 7
T C 7 S H 0 8 F U
2
1
4
RM- RM+ IR_OUT DC_TRG1
R 8 0 3
1 0 K
R 8 6 4
3 3
R 8 9 1
3 3
Q 7 6 2
C 4 0 8 1 U B T L R
+ 3 . 3 S
Q 7 6 1
A 1 5 7 6 U B T L R
R901
100K
D G N D
FHDMI_N_INT
C 8 0 0
1 0 0 0 P ( B )
MHL_VBUS_PRT
HSW2_N_INT
MHLVB_PON
HTX2_AUSEL
9 7 B C
I H P
0 0 0 9 3 B V
1 2 3 4
P L 3 . 0
P L 0 . 3
0
J753 J754
no_use
ZADC_N_PDWN
HDMI_PON
C 8 4 9
n o _ u s e
C 8 5 0
n o _ u s e
C 8 5 1
n o _ u s e
Q 7 6 4
n o _ u s e
+ 3 . 3 S
0
J755
Q 7 6 5
A 1 5 7 6 U B T L R
D G N D
L752
BLM21PG600SN1D
Z o n e 2
S u r . B a c k
S u r r o u n d /
S u b w o o f e r
M a i n Z o n e
( 5 C H )
232C_MOSI DGND +3.3M 232C_MISO
t o D I G I T A L ( 3 )
R S - 2 3 2 C
L3_DET
THM4
PS3_PRT
DEST
AMP_OLV
MODE
FLD_N_RST FLD_MOSI MIC_N_DET FLD_N_CS
D [ 6 ]
P 1 8 _ 7
INT1
A[9]
P 1 3 _ 7
DA0
TA4IN
V C C
A[1]
V S S
SDA5
T X D 0
TA2IN
D G N D
P17_7
SCL2
A[6] RXD9 A[0] A[10] D[14] A[11] A[15]
S D A 2
INT6
D [ 0 ]
P18_1
+ 3 . 3 M
A V C C
VSS
INT7
N C ( B C 1 )
D [ 8 ]
TA2IN
P 1 0 _ 7
P9_0
P 1 9 _ 5
D [ 3 ]
P 1 2 _ 7
P11_5
NSD
D G B _ N _ C E
P12_4
XOUT
D[9]
VDC1
V S S
R X D 1
P 1 1 _ 1
A[5]
C S 0
SCL5
A[7]
D B G _ S C K
A[8]
D B G _ E P M
A[16]
P14_1 P18_0
D [ 4 ]
D[13]
RSTMSK
A[4]
A [ 2 0 ]
C L K 1
P 1 3 _ 2
RST#
T H M
A[3]
D [ 7 ]
P14_3
N C ( B C L K )
E E P R O M
A[12]
P 1 0 _ 0
VDC0
NMI
A[2]
INT8 P7_2
P 6 _ 0
VCC
TA3IN
D [ 5 ]
A[18]
M C P U _ N _ R S T
t o M A I N ( 1 )
A[14]
GND
+ 3 . 3 M
D B G _ M I S O
GND
XIN
CNVSS
V R E F
P19_7
GND
P8_6
D [ 2 ]
I S C L K 2
NC
D B G _ M O S I
P 1 2 _ 6
A [ 2 2 ]
I I O 0 _ 1
VCC2
SDA3
N C
to Programmer to E8a P19_6
P 6 _ 4
D[15]
R X D 0
P 1 9 _ 1
V C C
P11_6
P 1 4 _ 7
T X D 1
TXD9
VCC1
CLK9 D[10]
to 003.sht (FPGA)
P8_7
A[17]
P 1 1 _ 0
D [ 1 ]
+ 3 . 3 S
C L K 0
Destination
A V S S
D[12]
INT2
A[13]
SCL3
N S D
A[19]
NC
D B G _ B U S Y
VCC
VSS D[11]
P9_5 P9_4
A [ 2 1 ]
D B G _ C N V S S
P 1 1 _ 2
NSD
INT0
P 1 1 _ 7
RESET
A 1 4
V S S
C E
A 1
A 9
R Y / B Y
B Y T E
D Q 1 5
D Q 1 1
A 7
A 1 8
A 0
A 1 2
A 1 3
D Q 4
A 4
V S S
A 2 1
D Q 2
A 2
D Q 1 0
D Q 9
D Q 8
D Q 1 3
A 1 9
A 6
A 8
D Q 0
V C C
A 1 5
A 1 1
D Q 1 4 A 1 0
W E
D Q 5
A 1 7
D Q 1
D Q 6
A 5
W P # / A A C
D Q 1 2 A 2 0
R E S E T
O E
A 3
D Q 3
D Q 7
A 1 6
P17_6 P17_5 P17_4
I S R X D 2
I S T X D 2
P 1 9 _ 4
C S 3
C S 2
P 5 _ 5
C S 1
P 1 3 _ 3
P 1 3 _ 0
R D
W R
P 5 _ 0
P 1 2 _ 5
P 1 9 _ 3
P 1 7 _ 3
P 1 7 _ 2
P 1 7 _ 1
P 1 7 _ 0
P 1 9 _ 2
TXD10 RXD10 CLK10 P16_4 P16_0 P12_3 P12_2 CLK6 TXD6
P 1 1 _ 4
P 1 9 _ 0
P 1 1 _ 3
P 1 8 _ 6
P 1 8 _ 4
P 1 8 _ 5
P 1 8 _ 3
P 1 8 _ 2
P 1 5 _ 7
P 1 5 _ 6
P 1 5 _ 5
P 1 5 _ 4
A N _ 6
A N _ 5
P 1 0 _ 4
P 1 0 _ 3
A N _ 2
A N _ 1
S C L 4
R X D 4
SDA4 TXD4
MODEL
t o O P E ( 2 )
1
M
H
T
T
R
P
_
C
D
THM2 THM3
PS2_PRT PS1_PRT
STBY_LED
t o O P E ( 1 )
FLD_PON KY_AD1 VDL_RA PSW_DET FLD_SCK REM_IN1 RM- KY_AD2 DGND ISEL_RA RM+ DGND +5.5 +5.5 +3.3M VDL_RB DGND ISEL_RB PD_LED
P 1 5 _ 3
USB_VBUS_PRT MODEL
A 8 3 0 o n l y
-
3 . 0 V 0 . 3 V
P U e d i n T u n e r
t o 0 0 8 . s h t
( P o w e r ) t o 0 0 7 . s h t
( D S P / D I R ) t o 0 0 1 . s h t
( H D M I R x ) t o 0 0 6 . s h t
( N e t / U S B )
t o 0 0 2 . s h t
( V D e c )
t o 0 0 4 . s h t
( H D M I T x ) t o 0 0 3 . s h t
( F P G A )
PS2_PRT
I C / C B / X L : 7 5 - 9 9
O H T E R : 7 5 0 - 9 9 9
S h e e t 5 : u - C o m
D I A G _ C H E C K
P 1 5 _ 2
P 1 5 _ 0
P7_4
P 1 3 _ 1
1 s t M P
M X I C B l a n k : X 9 6 9 7 B 0 M X 2 9 L V 6 4 0 E B T I - 7 0 G
E O N B l a n k : Y C 0 7 9 B 0 E N 2 9 L V 6 4 0 A B - 9 0 T I P
S T M i c r o Y D 8 5 3 A 0 M 9 5 5 1 2 - R D W 6 T P / K
R e n e s a s Y D 3 5 5 A 0 R 1 E X 2 5 5 1 2 A T A 0 0 A
( 2 1 2 5 )
(0.5%)
(0.5%)
W r i t t e n b y Y E M : Y F 2 5 3 A 0
1 s t M P
DCDC_PON R_200_DET SP_IMP PS2_PRT PS1_PRT AMP_LMT AMP_OLV I_PRT DC_PRT VOL_SCK MG VOL_MOSI SPRY_5CH HPRY SPRY_Z2 THM3_PRT MUTE_SB MUTE_Z2 MUTE_SW MUTE_5CH HP_N_DET SPRY_SB DCDC_PON TU_SDA TU_SCL TUN_N_INT TU_N_RST VID_SDA VID_SCL PS2_PRT L3_DET VID_PON VE VE VE ADCVBS ADY +3.3V ADPb ADPr +3.3S DGND THM1 THM2
t o M A I N ( 1 )
t o 0 0 2 . s h t
( V D e c )
MHL_VBUS_PRT
A 8 3 0 o n l y
E x c e p t A 8 3 0
S T M i c r o Y D 8 5 3 B 0 M 9 5 5 1 2 - R D W 6 T P / K
REMARKS
CAPACITOR
PARTS NAME
NO
NO
MARK
MARK
ELECTROLYTIC CAPACITOR
CERAMIC CAPACITOR
POLYESTER FILM CAPACITOR
POLYSTYRENE FILM CAPACITOR
MICA CAPACITOR
POLYPROPYLENE FILM CAPACITOR
SEMICONDUCTIVE CERAMIC CAPACITOR
P
TANTALUM CAPACITOR
TUBULAR
S
CAPACITOR CERAMIC
FILM SULFIDE POLYPHENYLENE
CAPACITOR
RESISTOR
REMARKS
NO MARK
PARTS NAME
CARBON
CARBON
METAL
METAL
METAL
FIRE
CEMENT
SEMI
FILM RESISTOR
FILM RESISTOR
OXIDE FILM RESISTOR
FILM RESISTOR
PLATE RESISTOR
PROOF CARBON FILM RESISTOR
MOLDED RESISTOR
VARIABLE RESISTOR
(P=5)
(P=10)
CHIP RESISTOR
NOTICE
U.S.A
G
CANADA
EUROPE
L
CHINA
AUSTRALIA
SINGAPORE
KOREA
GENERAL
U
C
T
A
K
R
JAPAN
(model)
B BRITISH
J
SOUTH EUROPE E
V TAIWAN
F RUSSIAN
P LATIN AMERICA
S BRAZIL
H THAI
IC82 : R1EX25512ATA00A
64 K word x 8-bit serial peripheral interface EEPROM
Vcc 8
Vss
4
S
1
W 3
C 6
Serial-parallel converter
Y-select and Sense amp.
Memory array
High voltage generator
HOLD
7
D
5
Q
2
Control logic
Address generator
Y decoder
X decoder
IC83 : R5F6416MADFE
Single chip 32-bit microprocessor
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
8 8 8 8 8 8 8
Port P8
Port P10
Port P11
8
8
Peripheral functions
Port P15 Port P16 Port P13 Port P14 P14_1
8 8 8 5
Port P17
8
Port P18
8
Port P19
8
Clock generator:
4 circuits
- XIN-XOUT
- XCIN-XCOUT
- On-chip oscillator
- PLL frequency synthesizer
Watchdog timer:
15 bits
DMAC
DMAC II
X-Y converter:
16 bits × 16 bits
CRC calculator (CCITT)
X 16 + X 12 + X 5 + 1
Serial interface:
11
channels
Timer:
Timer A16 bits × 5 timers
Timer B16 bits × 6 timers
Three-phase motor
controller
D/A converter:
8 bits × 2 channels
A/D converter:
10 bits × 1 circuit
Standard: 10 inputs
Maximum: 34 inputs
Intelligent I/O
Time Measurement: 16
Wave generation: 24
Serial interface:
- Variable-length
synchronous serial I/O
- IEBus
R32C/100 Series Microprocessor Core
R2R0
R3R1
R6R4
R7R5
A0
A1
A2
A3
FB
SB
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Memory
ROM
RAM
Multiplier
Floating-point unit
R2R0
R3R1
R6R4
R7R5
A0
A1
A2
A3
FB
SB
Port P7
8
7
P8_5
Port P9
8
Port P12
8
Multi-master I
2
C-bus
interface:
1 channel
V
DD
CE
Vref
4 3
1 2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC84, 85 : RP130Q331D-TR-F
Voltage regulator
IC92 : SN74LVC1G17DCKR
Single schmitt-trigger buffer
1
2
3
5
4
NC
A
GND
VCC
Y
INPUT
A
OUTPUT
Y
L
H
L
H
1
3
2
5
4
GND
V
CC
IN A
IN B
OUT Y
A
H
L
H
L
H
L
L
H H
H
H
L
B Y
1
3
2
5
4 GND
V
CC
IC80 : TC7SH32FU
2-input OR gate
IN A
IN B
OUT Y
IC93 : TC7WH126FU
Dual bus buffer
1 G1
2 A1
3 Y2
4 GND
8 Vcc
7 G2
6 Y1
5 A2
IC79, 81 : TC74VHC273FT (EL,K)
Octal D-type flip-flop with clear
1 CLR
Q1
Q2
Q3
Q4
GND
D1
D2
D3
D4
2
3
4
5
6
7
8
9
10
D CK CLR
L
H
H
H
X X
L
H
X
1
11
3
2
D R
CK Q
D1
Q1
CLR
CK
Q
L
L
H
Qn
Inputs Output
Function
Clear
−
−
No Change
20 VCC
Q8
Q7
Q6
Q5
CK
D8
D7
D6
D5
19
18
17
16
15
14
13
12
11
4
5
D R
CK Q
D2
Q2
7
6
D R
CK Q
D3
Q3
8
9
D R
CK Q
D4
Q4
13
12
D R
CK Q
D5
Q5
14
15
D R
CK Q
D6
Q6
17
16
D R
CK Q
D7
Q7
18
19
D R
CK Q
D8
Q8
A
L
L
H
H
L
L
L
H H
H
L
H
B Y
1
3
2
5
4
GND
V
CC
IC91 : TC7SH86FU
Exclusive OR gate
IN A
IN B
OUT Y
IC76, 78 : SN74LV4051APWR
8-channel analog multiplexers/demultiplexers
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
COM
INH
C
B
A
11
10
9
6
3
13
14
15
12
1
5
2
4
1
2
3
4
5
6
7
8 9
10
16
15
14
13
12
11
Y4
Y6
COM
Y7
Y5
INH
GND
GND
V
CC
Y2
Y1
Y0
Y3
A
B
C
INPUTS ON
CHANNEL
INH
L
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
X
C
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
L
Y1
Y2
Y3
Y4
Y5
Y6
Y7
None
Y0
B A
IC77 : EN29LV640AB-90TIP
64 M-bit flash memory boot sector flash memory, CMOS 3.0 volt-only
State
Control
Timer Vcc Detector
OE#
A0-A21
CE#
WE#
Vcc
Vss
RY/BY#
STB
STB
Y-Decoder Y-Gating
Data Latch
Input/Output Buffers
Chip Enable
Output Enable
Logic
Cell Matrix
X-Decoder
Address Latch
Command
Register
Program Voltage
Generator
Erase Voltage Generator
Block Protect Switches
28
1-10,13,16-25,48
26
11
15
29-36,38-45
DQ0-DQ15(A-1)
IC75, 87 : TC7SH08FU
2-input AND gate
to DIGITAL 1/8
to DIGITAL 2/8
to DIGITAL 2/8
to DIGITAL 3/8 to DIGITAL 6/8 to DIGITAL 7/8 to DIGITAL 8/8 to DIGITAL 4/8
DIGITAL (1)
No replacement part available.
MICROPROCESSOR
EEPROM
DFF1
FLASH ROM
ANALOG
MUX
to DIGITAL 3/8
to OPERATION (2)_CB344
(RX-V675/HTR-6066/TSR-6750)
Page 136 E9
to OPERATION (2)_CB344
(RX-A730)
Page 139 E9
to OPERATION (1)_CB303
(RX-V675/HTR-6066/TSR-6750)
Page 135 H9
to OPERATION (1)_CB304
(RX-A730)
Page 138 F10
to MAIN (1)_W109
Page 142 K7
to MAIN (1)_W108
Page 141 J6
to MAIN (3)_W112
Page 141 J7
(Writing port)
RX-A730
RX-V675/HTR-6066/TSR-6750