Yamaha RX-V2400, Service Manual

Page: 56 / 147

RX-V2400/RX-V2400RDS/DSP-AX2400
RX-V1400/RX-V1400RDS/HTR-5690/DSP-AX1400
RX-V2400/RX-V2400RDS/DSP-AX2400
RX-V1400/RX-V1400RDS/HTR-5690/DSP-AX1400
56
No. Name I/O Function
1 GP0[4]/(EXT̲INT4) IOZ General purpose I/O0 port 4
2 GP0[6]/(EXT̲INT6) IOZ General purpose I/O0 port 6
3 CVDD S
1.2V power supply
4 VSS GND
Ground
5 DVDD S 3.3V power supply
6 GP0[5]/(EXT̲INT5) IOZ General purpose I/O0 port 5
7 GP0[7]/(EXT̲INT7) IOZ
General purpose I/O0 port 7
8 CLKS1 I
McBSP1 external clock source
9 DVDD S 3.3V power supply
10 VSS GND Ground
11 CVDD S 1.2V power supply
12 TINP1/AHCLKX0 I
Timer 1 Input
13 TOUT1/AXRO[4]/AXR1[11] O Timer 1 Output
14 CVDD S 1.2V power supply
15 VSS GND
Ground
16 CLKX0/ACLKX0 IOZ
McASP0 Transmission BCLK
17 TINP0/AXRO[3]/AXR1[12] I Timer 0 Input
18 TOUT0/AXRO[2]/AXR1[13] O Timer 0 Output
19 ACLKR0 IOZ
McASP0 Reception BCLK
20 AXRO[1] IOZ
McASP0 Transmission/reception data 1
21 AFSX0 IOZ McASP0 Transmission LRCLK
22 CVDD S 1.2V power supply
23 VSS GND Ground
24 AFSR0 IOZ
McASP0 Reception LRCLK
25 DVDD S 3.3V power supply
26 VSS GND Ground
27 AXRO[0] IOZ
McASP0 Transmission/reception data 0
28 AHCLKR0 I
McASP0 Reception MCLK
29 CVDD S 1.2V power supply
30 VSS GND Ground
31 FSX1 IOZ
McBSP1 Transmission Frame Sync (Input in SPI slave state)
32 DX1 O/Z
McBSP1 Transmission data
33 CLKX1 IOZ McBSP1 Transmission clock (Input in SPI slave state)
34 VSS GND Ground
35 CVDD S 1.2V power supply
36 CLKR1 IOZ
McBSP1 Reception clock
37 DR1 I McBSP1 Reception data
38 FSR1 IOZ McBSP1 Reception Frame Sync
39 VSS GND
Ground
40 CVDD S
1.2V power supply
IC512: D601A002PYP180 (DSP P.C.B)
Decoder
Pin Multiple
xing
EMIF32
L1P Cache
Direct Mapped
4K Bytes Total
Digital Signal Processors
L1D Cache
2-Way Set
Associative
4K Bytes Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
Power-Down
Logic
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path B Data Path A
B Register File
Control
Registers
C67x TM CPU
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Test
A Register File
.L1t
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
.S1t .M1t .D1 .D2 .M2t .S2t .L2t
GP1
GP0
HPI16
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
Total