MOTIF XS6/MOTIF XS7/MOTIF XS8
66
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
OUTER
NO.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D4
D5
D6
D7
D8
VSS3OP
SRAM_WE
GPIO4/SRAM_READY
I2C_CLK
UART0_TX
TRST
TDI
SCMO
RESET
TCB[6]
TCA[6]
VDD3OP
VSS3I
VDD3OP
TCB[1]
TCA[0]
REFI
I2S_RX0_D3
I2S_RX0_BICK
I2S_RX0_MCK
D0
SRAM_BS[1]
SRAM_BS[0]
CS0
UART1_RX
VDD1IH
TDO
TMS
PLLE
VDD3OP
TCA[5]
TCB[4]
TCB[3]
TCB[2]
TCA[1]
FS32
I2S_RX0_D0
I2S_RX0_LRCK
I2S_TX0_D3
I2S_TX0_D1
D5
D1
SRAM_OE
CS3/EN4_B/GPIO6
I2C_DATA
UART1_TX
VSS3I
TCK
NLIG
TCA[7]
TCB[5]
TCA[4]
TCA[3]
TCA[2]
TCB[0]
REFO
I2S_RX0_D1
I2S_TX0_D2
I2S_TX0_D0
GPIO7/ I2S_TX0_MCK
D6
D2
D3
VSS3OP
CS2/EN4_A/GPIO5
VDD3OP
UART0_RX
VSS3OP
–
O
I/O
I/O
O
I
I
I
I
O
O
–
–
–
O
O
I
I
O
O
I/O
O
O
O
I
–
O
I
I
–
O
O
O
O
O
O
I
O
O
O
I/O
I/O
O
I/O
I/O
O
–
I
I
O
O
O
O
O
O
O
I
O
O
I/O
I/O
I/O
I/O
–
I/O
–
I
–
I/O ground
SRAM write enable
General purpose I/O / SRAM ready (read enable)
I2C Clock
Serial output
JTAG - Test reset (active low)
JTAG - Test data in
Scan mode select
Reset - active low
Test pin
Test pin
I/O 3.3V
Core ground
I/O 3.3V
Test pin
I2S Receiver 0 Data (ch.6/7)
I2S Receiver 0 Bit clock
I2S Receiver 0 Master clock
Data bus
SRAM upper byte select
SRAM lower byte select
Chip select
Serial intput
Core 1.8V
JTAG - Test data out
JTAG - Test mode select
PLL enable
I/O 3.3V
Test pin
I2S Receiver 0 Data (ch.0/1)
I2S Receiver 0 Left/Right clock
I2S Transmitter 0 Data ch.6/7
I2S Transmitter 0 Data ch.2/3
Data bus
SRAM output enable
Chip select / Rotary encoder input / General purpose I/O
I2C Data
Serial output
Core ground
JTAG - Test clock
Ignore PLL no-lock before releasing reset, active high.
Test pin
I2S Receiver 0 Data (ch.2/3)
I2S Transmitter 0 Data ch.4/5
I2S Transmitter 0 Data ch.0/1
General purpose I/O / I2S Transmitter 0 Master clock
Data bus
I/O ground
Chip select / Rotary encoder input / General purpose I/O
I/O 3.3V
Serial intput
I/O ground
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
OUTER
NO.
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E1
E2
E3
E4
E17
E18
E19
E20
F1
F2
F3
F4
F17
F18
F19
F20
G1
G2
G3
G4
G17
G18
G19
G20
H1
H2
H3
H4
H17
H18
H19
H20
J1
J2
J3
J4
J9
J10
J11
J12
J17
J18
J19
J20
K1
K2
K3
K4
K9
K10
K11
K12
K17
K18
K19
K20
TEMO
TCB[7]
VDD3OP
VDD1IH
VSS3OP
VDD3OP
VDD3OP
I2S_RX0_D2
VSS3OP
GPIO9/ I2S_TX0_LRCLK
VDD1IH
I2S_RX1_D1
D9
D8
D7
D4
GPIO8/I2S_TX0_BICK
VSS3I
I2S_RX1_D0
I2S_RX1_MCK
D13
D12
D10
VDD3OP
VDD3OP
I2S_RX1_LRCK
I2S_TX1_D1
I2S_TX1_LRCLK
VSS3I
D15
D14
D11
I2S_RX1_BICK
I2S_TX1_D0
I2S_TX1_BICK
I2S_TX1_MCK
A1
A0
VDD1IH
VSS3OP
VSS3OP
I2S_RX2_D1
I2S_RX2_D0
I2S_RX2_LRCK
A5
A4
A3
A2
VSS3OP
VSS3OP
VSS3OP
VSS3OP
I2S_RX2_BICK
I2S_RX2_MCK
I2S_TX2_D1
I2S_TX2_D0
A8
A6
A7
VDD3OP
VSS3OP
VSS3OP
VSS3OP
VSS3OP
GPIO12/I2S_TX2_LRCLK
GPIO11/I2S_TX2_BICK
GPIO10/I2S_TX2_MCK
HPX1
I
O
–
–
–
–
–
I
–
I/O
–
I
I/O
I/O
I/O
I/O
I/O
–
I
O
I/O
I/O
I/O
–
–
O
O
O
–
I/O
I/O
I/O
O
O
O
O
O
O
–
–
–
I
I
O
O
O
O
O
–
–
–
–
O
O
O
O
O
O
O
–
–
–
–
–
I/O
I/O
I/O
O
Test mode pin
Test pin
I/O 3.3V
Core 1.8V
I/O ground
I/O 3.3V
I2S Receiver 0 Data (ch.4/5)
I/O ground
General purpose I/O / I2S Transmitter 0 Left/Right clock
Core 1.8V
I2S Receiver 1 Data (ch.2/3)
Data bus
General purpose I/O / I2S Transmitter 0 Bit clock
Core ground
I2S Receiver 1 Data (ch.0/1)
I2S Receiver 1 Master clock
Data bus
I/O 3.3V
I2S Receiver 1 Left/Right clock
I2S Transmitter 1 Data ch.2/3
I2S Transmitter 1 Left/Right clock
Core ground
Data bus
I2S Receiver 1 Bit clock
I2S Transmitter 1 Data ch.0/1
I2S Transmitter 1 Bit clock
I2S Transmitter 1 Master clock
Address bus
Core 1.8V
I/O ground
I2S Receiver 2 Data (ch.2/3)
I2S Receiver 2 Data (ch.0/1)
I2S Receiver 2 Left/Right clock
Address bus
I/O ground
I2S Receiver 2 Bit clock
I2S Receiver 2 Master clock
I2S Transmitter 2 Data ch.2/3
I2S Transmitter 2 Data ch.0/1
Address bus
I/O 3.3V
I/O ground
General purpose I/O / I2S Transmitter 2 Left/Right clock
General purpose I/O / I2S Transmitter 2 Bit clock
General purpose I/O / I2S Transmitter 2 Master clock
GPIO(Z)
1394AV-L
(X6893A00)
DICE
II
