Yamaha DSP-AX1/RX-V1, Service Manual

Page: 80 / 120

A B C D E F G H
1
2
3
4
5
6
I J K L
7
8
DSP-AX1/RX-V1
SUPER IMPOSE
0
0
0
0
-0.1
0
0
0
0
0
0
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
0
-0.1
-0.1
1.4
1.4
0
0
4.9
4.9
0
0
-4.9
0
0
-0.1
0
-0.1
0
-0.1
0
-0.1
0
-0.1
0
0
0
0
0
-0.1
4.9
4.9
4.9
-4.9
4.1
0
-4.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.9
4.9
0
0
-4.9
0
0 0
4.9
2.6
4.4
4.9
4.2
-1.3
-0.6
0.4
4.9
0
0
0
4.9
0
1.2
-0.1
-0.7
-0.6
-0.6
4.9
0 0
2.2
4.8
2.2 4.8 4.8 4.9
0
2.3
4.9
1.4
2.0
4.9
4.9
4.9
4.9
1.4
1.4
0.7
0
0
0
0
4.9
4.7
1.4
1.4 1.4
2.1
2.0
2.3 4.8 4.8
0.3
4.9
4.9
4.9
4.9 2.0
0
0
0
4.8
0
4.8
4.3
-0.5
4.2
1.5
1.5
0.7
0
0
0
0
0
4.2 4.2
4.9
4.4
4.3
0 0
0
0
2.6 2.6 2.6
2.6
0
4.4
-4.9
0
0 4.4
4.9
4.4
4.9
4.8
4.8
-4.9
4.9
4.8
4.8
-4.9
-4.9
-4.9
0
0
4.9
4.9
0
0
4.9
4.8
4.8
-4.9
0
0
-4.9
0
0
4.9
4.9
0
0
-4.9
0
0
0
4.9
4.4
4.2
4
.7
4.2
4.2
4.2
0 0
0
0
0.3
4.9
4.9
0
4.9
0 0 0 0
0
i
CIRCUIT CHANGES BY MARKET.
X : NOT USED
■
SCHEMATIC DIAGRAM (VIDEO)
* All voltage are measured with a 10M
Ω
/V DC electric volt meter.
* Components having special characteristics are marked
Z
and
must be replaced with parts having specifications equal to those
originally installed.
* Schematic diagram is subject to change without notice.
Point
i
(Pin 16 of IC12)
V : 2V/div, H : 50 nsec/div
DC, 1 : 1 probe
0V
LEVEL
CONVERTER
BINARY TO 1-OF-8
DECODER WITH INHIBIT
11
10
9
8
7
6 16
13 SW
SW
SW
SW
SW
SW
SW
SW
14
15
12
1
5
2
4
3
INHIBIT VDD
X
A
B
C
VSS
VEE
X0
X1
X2
X3
X4
X5
X6
X7
IC4~7 : TC74HC4051AP
Analog Multiplexer/Demultiplexer
INPUT STATES
INHIBIT
0
0
0
0
0
0
0
0
1
C
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
X
“ON” CHANNEL (S)
0
1
2
3
4
5
6
7
NONE
IC13, 14 : TC74HCUO4AP
Hex Inverters
1A
1Y
2Y
V
DD
6A
1
2
3
4 11
2A 6Y
5A
12
13
14
3A
3Y
5Y
4A
5
6
7 V
SS
4Y 8
9
10
IC8, 9 : TC74HC4053AP
Triple 2-Channel Multiplexer/Demultiplexer
16
VDD
LOGIC LEVEL
CONVER
TER
12
OX
7
VEE
6
INH
OUT C IN
13
IX
OUT C IN
2
OY
OUT C IN
1 IY OUT C IN
5 OZ OUT C IN
3
IZ OUT C IN
4
Z-COMMON
15
14
X-COMMON
Y-COMMON
9 C
10
B
11
A
8
VSS
INHIBIT
(Pin 6)
L
L
L
L
L
L
L
L
H
CONTROL INPUTS “ON” CHANNEL
0X (Pin 12), 0Y (Pin 2), 0Z (Pin 5)
1X (Pin 13), 1Y (Pin 1), 1Z (Pin 3)
0X, 0Y, 0Z
1X, 0Y, 0Z
0X, 1Y, 0Z
1X, 1Y, 0Z
0X, 0Y, 1Z
1X, 0Y, 1Z
0X, 1Y, 1Z
1X, 1Y, 1Z
NOTE
C
(Pin 9)
L
L
L
L
H
H
H
H
*
B
(Pin 10)
L
L
H
H
L
L
H
H
*
A
(Pin 11)
L
H
L
H
L
H
L
H
*
* Don’t Care
IC1, 10, 11 : LA7108M
75
Ω
Video Driver
6dB DR
6dB DR
6dB DR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN1+
NFB1
MUTE1
VIN2+
NFB2
–VCC1
VIN3+
NFB3
+VCC
VOUT1
GND
VOUT2
MUTE2
VOUT3
MUTE3
–VCC2
IC15 : BU2092
Serial In/Parallel Out Driver
CONTROL
CIRCUIT
OUTPUT
BUFFER (OPEN DRAIN)
128BIT
STRAGE RESISTER
128BIT
SHIFT
RESISTER
10
11
12
13
14
15
16
17
18
VSS
DATA
CLOCK
LCK
Q0
Q1
Q2
Q3
Q4
VDD
OE
Q11
Q10
Q9
Q8
Q7
Q6
Q5
1
2
3
4
5
6
7
8
9
E-95/J-87
P-E97/J89
F-1
P-E96/J88
F-1
P-E93/J85
D-3
P-E99/J91
G-1
P-E96/J88
D-6
P-E92/J84
K-8
P-E92/J84
K-6
P-E92/J84
K-6