xiQ - Technical Manual Version 1.0
41
3.8.3.5.
Digital Input – Timing
Typical measured input delay between Digital Input to FPGA Input
Measurements of input delays:
Edge Type
Input Voltage [V]
Typ. delay [μs]
Rising
15
1.4
Rising
20
0.6
Falling
15
5.3
Falling
20
7.8
table 3-25, digital input, timing
Note:
•
Measured at: Ambient Temperature 25°C
3.8.4.
Digital Output
3.8.4.1.
Digital Output - General info
Item
Parameter / note
Indicator
Yes, must be configured by user to Status 1 LED
Output port type
Open collector NPN
Protection
short-circuit / over-current / Reverse voltage
Protection circuit
PTC Resettable Fuse
Effect of incorrect output terminal connection
Not protected against reverse voltage connection
Inductive loads
no
Maximal output dropout
1.8V, Sink current 25mA
table 3-26, digital output, general info
3.8.4.2.
Digital Output – signal levels
Output levels definition
State
Open Collector Switch State
R [Ohm]
Conditions
On (1)
ON - Transistor is conducting
max. 160
For output > 5mA
Off (0)
OFF - Transistor is not conducting
min 100 k
table 3-27, digital output, signal levels
Maximum sink current: 25 mA
Maximum open circuit voltage: 24V
