xiQ - Technical Manual Version 1.35
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3.9.3.4.
Digital Input – 5V logic
Digital Input 5V – signal levels
Depending on the camera's hardware version two different input signal levels are supported.
Input levels are not IEC 61131-2, Type 1 as the ON state has been extended to support 5V TTL.
V-in-min [V]
V-in-max [V]
State
I [mA]
-24.0
2.0
Off (0)
0.0 – 0.3 mA (0mA nominal)
2.0
4.0
Transient
4
4.0
24.0
On (1)
4 – 6 mA (5mA nominal)
table 3-31, digital info, signal levels, 5V logic
Note:
•
Input level Vin represents amplitude of the input signal.
•
Voltage levels referenced to common ground GND
Digital Input 5V – Internal Schematic
Following scheme is internal scheme of Digital Input signal flow inside the camera.
figure 3-39, digital input, interface schematic, 5V logic
Digital Input 5V – Timing
Typical measured input delay between Digital Input to FPGA Input
Measurements of input delays:
Edge Type
Input Voltage [V]
Typ. delay [μs]
Rising
5
1.6
Rising
10
1.7
Falling
5
7.8
Falling
10
10.7
Falling
24
12.7
table 3-32, digital input, timing, 5V logic
Note:
•
Measured at: Ambient Temperature 25°C
VCC
DIGITAL IN PUT
IINPUT
FPG A_IN PUT
GND (Comm on IO Gr oun d)
6
2
0
R
1
0
0
R
1
0
K
4
9
K
9
GND
