Xilinx Vivado MIPI CSI-2, Product Manual

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MIPI CSI-2 RX Subsystem v4.0 44
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
Clocking
The subsystem clocks are described in Table 3-1 . Clock frequencies should be selected to
match the throughput requirement of the downstream video pipe IP cores.
The MIPI CSI-2 RX Subsystem clocking structure is illustrated in Figure 3-7 and Table 3-2 .
X-Ref Target - Figure 3-6
Figure 3-6: Subsystem Customization Screen - Pin Assignment
Table 3-1: Subsystem Clocks
Clock Name Description
lite_aclk
(1)
AXI4-Lite clock used by the register interface of all IP cores in the subsystem.
video_aclk
(2)
Clock used as core clock for all IP cores in the subsystem.
dphy_clk_200M
See the MIPI D-PHY LogiCORE IP Product Guide ( PG202 ) [Ref 3] for information
on this clock.
clkoutphy_out
The
clkoutphy_out
signal is generated within the PLL with 2500 Mb/s line
rate when the Include Shared logic in core option is selected.
clkoutphy_in
The
clkoutphy_in
signal should be connected to the
clkoutphy_out
signal
generated when the Include Shared logic in core option is selected.
Notes:
1. The lite_aclk clock should be less than or equal to video_aclk.
2. Maximum recommended video clock is 250 MHz for Ult devices and 175 MHz for 7 Series devices. If
required, a higher throughput can be achieved by increasing the Pixels per clock option from Single to Dual or
Quad.
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